On 3/24/2026 3:43 PM, Konrad Dybcio wrote: > On 3/23/26 9:12 PM, Akhil P Oommen wrote: >> Implement pwrup reglist support and add the necessary register >> configurations to enable IFPC support on A840 >> >> Signed-off-by: Akhil P Oommen <[email protected]> >> --- > > [...] > >> + for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_DDE_BV; pipe_id++) { >> + for (i = 0; i < dyn_pwrup_reglist->count; i++) { >> + if ((dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)) == >> 0) > > that's a nitty pet peeve, but I'd check for if (!(...)) instead > > [...] > >> + continue; >> + *dest++ = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe_id); >> + *dest++ = dyn_pwrup_reglist->regs[i].offset; >> + *dest++ = a8xx_read_pipe_slice(gpu, >> + pipe_id, >> + >> a8xx_get_first_slice(a6xx_gpu), > > Only the first slice?
Yeah. I think we just need to pass a valid slice id and a8xx_get_first_slice() will always return a valid one. > > [...] > >> + /* Lo address */ >> + OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); >> + /* Hi address */ >> + OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); >> + >> + /* Enable dyn pwrup list with triplets (offset, value, pipe) */ >> + OUT_RING(ring, BIT(31)); > > I believe you need to patch OUT_PKT7() with the updated cmd count Thanks. Fixed. I guess the mask was probably helping when I tested. -Akhil. > > Konrad
