On Wed, Apr 29, 2026 at 06:00:12PM +0100, Prabhakar wrote: > From: Lad Prabhakar <[email protected]> > > The RZ/T2H (R9A09G077) SoC includes a DU with a DPI interface, > supporting resolutions up to WXGA with two RPFs for layer blending. > Unlike earlier RZ/G2L SoCs, RZ/T2H requires explicit assertion of a > DPI output-enable signal (DU_MCR0_DPI_EN) during CRTC startup. > > Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]> > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 7 ++++++- > drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 14 ++++++++++++++ > drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 10 ++++++++++ > 3 files changed, 30 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c > index 2b772a11c7ee..017d5f26bc96 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c > @@ -28,6 +28,7 @@ > #include "rzg2l_du_vsp.h" > > #define DU_MCR0 0x00 > +#define DU_MCR0_DPI_EN BIT(0) > #define DU_MCR0_DI_EN BIT(8) > > #define DU_DITR0 0x10 > @@ -217,8 +218,12 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc > *rcrtc) > static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start) > { > struct rzg2l_du_device *rcdu = rcrtc->dev; > + u32 val = DU_MCR0_DI_EN; > > - writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0); > + if (start && rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_DPIO_OE)) > + val |= DU_MCR0_DPI_EN; > + > + writel(start ? val : 0, rcdu->mmio + DU_MCR0); > } > > static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc) > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > index 3b7162c6e1f4..fc55dfffebaf 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > @@ -63,10 +63,24 @@ static const struct rzg2l_du_device_info > rzg2l_du_r9a09g057_info = { > }, > }; > > +static const struct rzg2l_du_device_info rzg2l_du_r9a09g077_info = { > + .channels_mask = BIT(0), > + .routes = { > + [RZG2L_DU_OUTPUT_DPAD0] = { > + .possible_outputs = BIT(0), > + .port = 0, > + }, > + }, > + .features = RZG2L_DU_FEATURE_DPIO_OE, > + .mode_clock_min = 5000, > + .mode_clock_max = 100000, > +}; > + > static const struct of_device_id rzg2l_du_of_table[] = { > { .compatible = "renesas,r9a07g043u-du", .data = > &rzg2l_du_r9a07g043u_info }, > { .compatible = "renesas,r9a07g044-du", .data = > &rzg2l_du_r9a07g044_info }, > { .compatible = "renesas,r9a09g057-du", .data = > &rzg2l_du_r9a09g057_info }, > + { .compatible = "renesas,r9a09g077-du", .data = > &rzg2l_du_r9a09g077_info }, > { /* sentinel */ } > }; > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > index 885558eb9547..baf076d69cda 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > @@ -20,6 +20,8 @@ > struct device; > struct drm_property; > > +#define RZG2L_DU_FEATURE_DPIO_OE BIT(0) /* Has DPIO output enable > control */ > + > enum rzg2l_du_output { > RZG2L_DU_OUTPUT_DSI0, > RZG2L_DU_OUTPUT_DPAD0, > @@ -46,12 +48,14 @@ struct rzg2l_du_output_routing { > * @routes: array of CRTC to output routes, indexed by output > (RZG2L_DU_OUTPUT_*) > * @mode_clock_min: minimum pixel clock in kHz > * @mode_clock_max: maximum pixel clock in kHz > + * @features: device features (RZG2L_DU_FEATURE_*) > */ > struct rzg2l_du_device_info { > unsigned int channels_mask; > struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; > u32 mode_clock_min; > u32 mode_clock_max; > + unsigned int features; > }; > > #define RZG2L_DU_MAX_CRTCS 1 > @@ -77,6 +81,12 @@ static inline struct rzg2l_du_device > *to_rzg2l_du_device(struct drm_device *dev) > return container_of(dev, struct rzg2l_du_device, ddev); > } > > +static inline bool rzg2l_du_has(struct rzg2l_du_device *rcdu, > + unsigned int feature) > +{ > + return rcdu->info->features & feature; > +} > + > const char *rzg2l_du_output_name(enum rzg2l_du_output output); > > #endif /* __RZG2L_DU_DRV_H__ */ -- Regards, Laurent Pinchart
