Hi Conor,
On 5/13/2026 1:12 AM, Conor Dooley wrote:
On Tue, May 12, 2026 at 05:56:35PM +0800, Damon Ding wrote:
RK3588 eDP controller requires HCLK_VO1 (video output bus clock)
to access the VO1 GRF registers and enable the video datapath.
Previously, the clock was enabled implicitly via the 'rockchip,vo-grf'
phandle reference, which allowed the eDP to work without explicitly
managing the hclk_vo1 clock. However, this is not safe or explicit.
To align with other display controllers (HDMI) on RK3588 and make
the clock requirement explicit, expand clock-names to support either
"grf" (for older SoCs) or "hclk" (for RK3588) as the third clock.
This makes the clock dependency clear and removes reliance on implicit
clock enablement from GRF phandle.
Fixes: f855146263b1 ("dt-bindings: display: rockchip: analogix-dp: Add support for
RK3588")
Signed-off-by: Damon Ding <[email protected]>
---
Changes in v4:
- Modify the commit msg.
---
.../bindings/display/rockchip/rockchip,analogix-dp.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
index d99b23b88cc5..d2bc8636b626 100644
---
a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
+++
b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
@@ -26,7 +26,9 @@ properties:
items:
- const: dp
- const: pclk
- - const: grf
+ - enum:
+ - grf
+ - hclk
Could you also enforce the correct clock name on a per-compatible basis
please?
pw-bot: changes-requested
Yes, will do in v5.
power-domains:
maxItems: 1
--
2.34.1
Best regards,
Damon
