Add GPU and GMU devicetree nodes for the Adreno 810 GPU found on Qualcomm SM7635 (Milos) based devices.
The qcom,kaanapali-gxclkctl.h header can be reused here because Milos uses the same driver and the GX_CLKCTL_GX_GDSC definition is identical. Signed-off-by: Alexander Koskovich <[email protected]> --- arch/arm64/boot/dts/qcom/milos.dtsi | 165 ++++++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 0e7cfc12b0d2..71fff0f35093 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2025, Luca Weiss <[email protected]> */ +#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h> #include <dt-bindings/clock/qcom,milos-camcc.h> #include <dt-bindings/clock/qcom,milos-dispcc.h> #include <dt-bindings/clock/qcom,milos-gcc.h> @@ -1554,6 +1555,121 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-44010000", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x6c000>, + <0x0 0x03d9e000 0x0 0x2000>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; + + iommus = <&adreno_smmu 0 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <2136718>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0xc8295ffd>; + }; + + opp-362000000 { + opp-hz = /bits/ 64 <362000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <2136718>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0xc02c5ffd>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <3972656>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0x882b5ffd>; + }; + + opp-644000000 { + opp-hz = /bits/ 64 <644000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <5285156>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-688000000 { + opp-hz = /bits/ 64 <688000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <6074218>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-763000000 { + opp-hz = /bits/ 64 <763000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <6671875>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0xa8295ffd>; + }; + + opp-895000000 { + opp-hz = /bits/ 64 <895000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0x88295ffd>; + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0xa8285ffd>; + }; + + opp-1050000000 { + opp-hz = /bits/ 64 <1050000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <18597656>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0x88285ffd>; + }; + + opp-1150000000 { + opp-hz = /bits/ 64 <1150000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; + opp-peak-kBps = <18597656>; + opp-supported-hw = <0x3>; + qcom,opp-acd-level = <0xa02f5ffd>; + }; + }; + }; + gxclkctl: clock-controller@3d64000 { compatible = "qcom,milos-gxclkctl"; reg = <0x0 0x03d64000 0x0 0x6000>; @@ -1564,6 +1680,55 @@ gxclkctl: clock-controller@3d64000 { #power-domain-cells = <1>; }; + gmu: gmu@3d6c000 { + compatible = "qcom,adreno-gmu-810.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6c000 0x0 0x32000>; + reg-names = "gmu"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,milos-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; -- 2.53.0
