On Wed, May 20, 2026 at 1:36 AM Akhil P Oommen <[email protected]> wrote:
>
> On 5/19/2026 12:36 AM, Rob Clark wrote:
> > Pull in perfcntr json and wire up generation of perfcntr tables.
> >
> > Sync from mesa commit d2c4653ee953 ("freedreno/registers: Add gen8
> > perfcntrs")
> >
> > Signed-off-by: Rob Clark <[email protected]>
> > Reviewed-by: Dmitry Baryshkov <[email protected]>
> > Reviewed-by: Anna Maniscalco <[email protected]>
> > ---
> > drivers/gpu/drm/msm/Makefile | 25 +-
> > drivers/gpu/drm/msm/msm_perfcntr.h | 48 ++++
> > .../msm/registers/adreno/a2xx_perfcntrs.json | 109 ++++++++
> > .../msm/registers/adreno/a5xx_perfcntrs.json | 128 ++++++++++
> > .../msm/registers/adreno/a6xx_perfcntrs.json | 105 ++++++++
> > .../msm/registers/adreno/a7xx_perfcntrs.json | 228 +++++++++++++++++
> > .../msm/registers/adreno/a8xx_perfcntrs.json | 240 ++++++++++++++++++
> > 7 files changed, 882 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/msm/msm_perfcntr.h
> > create mode 100644 drivers/gpu/drm/msm/registers/adreno/a2xx_perfcntrs.json
> > create mode 100644 drivers/gpu/drm/msm/registers/adreno/a5xx_perfcntrs.json
> > create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
> > create mode 100644 drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
> > create mode 100644 drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
> >
>
> << snip >>
>
> > diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
> > b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
> > new file mode 100644
> > index 000000000000..8bb31820479e
> > --- /dev/null
> > +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
> > @@ -0,0 +1,105 @@
> > +{
>
> RBBM and CMP groups are missing here.
Yes, so far we only support the counters that mesa has been using.
There are some missing. Although RBBM and CMP look straightforward to
add.
> > + "chip": "A6XX",
> > + "groups": [
> > + {
> > + "name": "CP",
> > + "num": 14,
> > + "reserved": [ 0 ],
> > + "select": "CP_PERFCTR_CP_SEL",
> > + "counter": "RBBM_PERFCTR_CP",
> > + "countable_type": "a6xx_cp_perfcounter_select"
>
> << snip >>
>
> > diff --git a/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
> > b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
> > new file mode 100644
> > index 000000000000..e60aab1862ec
> > --- /dev/null
> > +++ b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
> > @@ -0,0 +1,228 @@
> > +{
> > + "chip": "A7XX",
> > + "groups": [
> > + {
> > + "name": "CP",
> > + "num": 14,
> > + "reserved": [ 0 ],
> > + "select": "CP_PERFCTR_CP_SEL",
> > + "counter": "RBBM_PERFCTR_CP",
> > + "countable_type": "a7xx_cp_perfcounter_select"
> > + },
> > + {
> > + "name": "RBBM",
> > + "num": 4,
> > + "select": "RBBM_PERFCTR_RBBM_SEL",
> > + "counter": "RBBM_PERFCTR_RBBM",
> > + "countable_type": "a7xx_rbbm_perfcounter_select"
> > + },
> > + {
> > + "name": "PC",
> > + "pipe": "BR",
> > + "num": 8,
> > + "select": "PC_PERFCTR_PC_SEL",
> > + "counter": "RBBM_PERFCTR_PC",
> > + "countable_type": "a7xx_pc_perfcounter_select"
> > + },
> > + {
> > + "name": "VFD",
> > + "pipe": "BR",
> > + "num": 8,
> > + "select": "VFD_PERFCTR_VFD_SEL",
> > + "counter": "RBBM_PERFCTR_VFD",
> > + "countable_type": "a7xx_vfd_perfcounter_select"
> > + },
> > + {
> > + "name": "HLSQ",
> > + "pipe": "BR",
> > + "num": 6,
> > + "select": "SP_PERFCTR_HLSQ_SEL",
> > + "counter": "RBBM_PERFCTR_HLSQ",
> > + "countable_type": "a7xx_hlsq_perfcounter_select"
> > + },
> > + {
> > + "name": "VPC",
> > + "pipe": "BR",
> > + "num": 6,
> > + "select": "VPC_PERFCTR_VPC_SEL",
> > + "counter": "RBBM_PERFCTR_VPC",
> > + "countable_type": "a7xx_vpc_perfcounter_select"
> > + },
> > + {
> > + "name": "TSE",
> > + "pipe": "BR",
> > + "num": 4,
> > + "select": "GRAS_PERFCTR_TSE_SEL",
> > + "counter": "RBBM_PERFCTR_TSE",
> > + "countable_type": "a7xx_tse_perfcounter_select"
> > + },
> > + {
> > + "name": "RAS",
> > + "pipe": "BR",
> > + "num": 4,
> > + "select": "GRAS_PERFCTR_RAS_SEL",
> > + "counter": "RBBM_PERFCTR_RAS",
> > + "countable_type": "a7xx_ras_perfcounter_select"
> > + },
> > + {
> > + "name": "UCHE",
> > + "num": 12,
>
> A740 and newer has 24 counters
We don't yet have a way of dealing with mid-gen changes like this.. I
have some ideas, but nothing implemented yet. The same situation
comes up for a8xx, where some new counter groups are added.
> > + "select": "UCHE_PERFCTR_UCHE_SEL",
> > + "counter": "RBBM_PERFCTR_UCHE",
> > + "countable_type": "a7xx_uche_perfcounter_select"
> > + },
>
> << snip >>
>
> > diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
> > b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
> > new file mode 100644
> > index 000000000000..503b113df397
> > --- /dev/null
> > +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
> > @@ -0,0 +1,240 @@
> > +{
> > + "chip": "A8XX",
> > + "groups": [
> > + {
> > + "name": "CP",
> > + "num": 14,
> > + "reserved": [ 0 ],
> > + "select": "CP_PERFCTR_CP_SEL",
> > + "counter": "RBBM_PERFCTR_CP",
> > + "countable_type": "a8xx_cp_perfcounter_select"
> > + },
> > + {
> > + "name": "RBBM",
> > + "num": 4,
> > + "select": "RBBM_PERFCTR_RBBM_SEL",
> > + "slice_select": [ "RBBM_SLICE_PERFCTR_RBBM_SEL" ],
> > + "counter": "RBBM_PERFCTR_RBBM",
> > + "countable_type": "a8xx_rbbm_perfcounter_select"
> > + },
> > + {
> > + "name": "PC",
> > + "pipe": "BR",
> > + "num": 8,
> > + "select": "PC_PERFCTR_PC_SEL",
> > + "slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ],
> > + "counter": "RBBM_PERFCTR_PC",
> > + "countable_type": "a8xx_pc_perfcounter_select"
> > + },
> > + {
> > + "name": "VFD",
> > + "pipe": "BR",
> > + "num": 8,
> > + "select": "VFD_PERFCTR_VFD_SEL",
> > + "counter": "RBBM_PERFCTR_VFD",
> > + "countable_type": "a8xx_vfd_perfcounter_select"
> > + },
> > + {
> > + "name": "HLSQ",
> > + "pipe": "BR",
> > + "num": 6,
> > + "select": "SP_PERFCTR_HLSQ_SEL",
> > + "slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ],
> > + "counter": "RBBM_PERFCTR_HLSQ",
> > + "countable_type": "a8xx_hlsq_perfcounter_select"
> > + },
> > + {
> > + "name": "VPC",
> > + "pipe": "BR",
> > + "num": 6,
> > + "select": "VPC_PERFCTR_VPC_SEL",
> > + "slice_select": [ "VPC_PERFCTR_VPC_SEL_1",
> > "VPC_PERFCTR_VPC_SEL_2" ],
> > + "counter": "RBBM_PERFCTR_VPC",
> > + "countable_type": "a8xx_vpc_perfcounter_select"
> > + },
> > + {
> > + "name": "TSE",
> > + "pipe": "BR",
> > + "num": 4,
> > + "select": "GRAS_PERFCTR_TSE_SEL",
> > + "slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ],
> > + "counter": "RBBM_PERFCTR_TSE",
> > + "countable_type": "a8xx_tse_perfcounter_select"
> > + },
> > + {
> > + "name": "RAS",
> > + "pipe": "BR",
> > + "num": 4,
> > + "select": "GRAS_PERFCTR_RAS_SEL",
> > + "counter": "RBBM_PERFCTR_RAS",
> > + "countable_type": "a8xx_ras_perfcounter_select"
> > + },
> > + {
> > + "name": "UCHE",
> > + "num": 12,
>
> "num": 24,
ack
>
> > + "select": "UCHE_PERFCTR_UCHE_SEL",
> > + "counter": "RBBM_PERFCTR_UCHE",
> > + "countable_type": "a8xx_uche_perfcounter_select"
> > + },
> > + {
> > + "name": "TP",
> > + "pipe": "BR",
> > + "num": 12,
> > + "select": "TPL1_PERFCTR_TP_SEL",
> > + "counter": "RBBM_PERFCTR_TP",
> > + "countable_type": "a8xx_tp_perfcounter_select"
> > + },
> > + {
> > + "name": "SP",
> > + "pipe": "BR",
> > + "num": 24,
> > + "select": "SP_PERFCTR_SP_SEL",
> > + "counter": "RBBM_PERFCTR_SP",
> > + "countable_type": "a8xx_sp_perfcounter_select"
> > + },
> > + {
> > + "name": "RB",
> > + "pipe": "BR",
> > + "num": 8,
> > + "select": "RB_PERFCTR_RB_SEL",
> > + "counter": "RBBM_PERFCTR_RB",
> > + "countable_type": "a8xx_rb_perfcounter_select"
> > + },
> > + {
> > + "name": "VSC",
> > + "num": 2,
> > + "select": "VSC_PERFCTR_VSC_SEL",
> > + "counter": "RBBM_PERFCTR_VSC",
> > + "countable_type": "a8xx_vsc_perfcounter_select"
> > + },
> > + {
> > + "name": "CCU",
> > + "pipe": "BR",
> > + "num": 5,
> > + "select": "RB_PERFCTR_CCU_SEL",
> > + "counter": "RBBM_PERFCTR_CCU",
> > + "countable_type": "a8xx_ccu_perfcounter_select"
> > + },
> > + {
> > + "name": "LRZ",
> > + "pipe": "BR",
> > + "num": 4,
> > + "select": "GRAS_PERFCTR_LRZ_SEL",
> > + "counter": "RBBM_PERFCTR_LRZ",
> > + "countable_type": "a8xx_lrz_perfcounter_select"
> > + },
> > + {
> > + "name": "CMP",
>
> "pipe": "BR",
ack
BR,
-R
