On 4/12/2026 1:59 AM, Dmitry Baryshkov wrote:
On Fri, Apr 10, 2026 at 05:33:49PM +0800, Yongxing Mou wrote:
From: Abhinav Kumar <[email protected]>
Introduce the `mst_streams` field in each DP controller descriptor to
specify the number of supported MST streams. Most platforms support 2 or
4 MST streams, while platforms without MST support default to a single
stream (`DEFAULT_STREAM_COUNT = 1`).
There is no such const anymore.
Also accounts for platforms with asymmetric stream support, e.g., DP0
supporting 4 streams and DP1 supporting 2.
There is no need to mention it.
Signed-off-by: Abhinav Kumar <[email protected]>
Signed-off-by: Yongxing Mou <[email protected]>
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 20 +++++++++++++++++---
drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 ++
drivers/gpu/drm/msm/dp/dp_display.c | 20 +++++++++++++++++++-
drivers/gpu/drm/msm/dp/dp_display.h | 1 +
4 files changed, 39 insertions(+), 4 deletions(-)
@@ -2740,7 +2741,8 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl
*msm_dp_ctrl)
if (rc)
return rc;
- for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
+ ctrl->num_pixel_clks = 0;
+ for (i = DP_STREAM_0; i < max_stream; i++) {
Why? I think the code was fine with getting up to DP_STREAM_MAX clocks.
Sure.. will change max_stream -> DP_STREAM_MAX next version.
In fact, I'd rather use that instead of the hardcoded value for
determining how many streams can be there. Think of the old DTs which
didn't have extra stream clocks. We still need to support those.
The current logic only assigns num streams to dp->max_stream when
desc->mst_streams == num_pixel_clks, otherwise set to 1 which mean sst.
I would like to introduce a switch in the driver to control the number
of streams, rather than having it fully determined by the DTs.
Do you think it would be acceptable to use:
dp->max_stream = min(num_pixel_clks, desc->mst_streams)?
ctrl->pixel_clk[i] = devm_clk_get(dev, pixel_clks[i]);
if (i == 0 && IS_ERR(ctrl->pixel_clk[i]))
@@ -2750,14 +2752,26 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl
*msm_dp_ctrl)
DRM_DEBUG_DP("stream %d pixel clock not exist", i);
break;
}
+
+ ctrl->num_pixel_clks++;
}
return 0;
}
@@ -1234,6 +1248,10 @@ static int msm_dp_display_probe(struct platform_device *pdev)
dp->msm_dp_display.is_edp =
(dp->msm_dp_display.connector_type == DRM_MODE_CONNECTOR_eDP);
dp->hpd_isr_status = 0;
+ dp->max_stream = 1;
+
+ if (desc->mst_streams > 1)
+ dp->max_stream = desc->mst_streams;
Here you can assign it from the DT resources.
mutex_init(&dp->plugged_lock);
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h
index a5c6ed5b18e4..b0cfdf215970 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -26,6 +26,7 @@ struct msm_dp {
bool psr_supported;
};
+int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display);
int msm_dp_display_get_modes(struct msm_dp *msm_dp_display);
bool msm_dp_display_check_video_test(struct msm_dp *msm_dp_display);
int msm_dp_display_get_test_bpp(struct msm_dp *msm_dp_display);
--
2.43.0
