Hi Tommaso, Thanks for the feedback.
> -----Original Message----- > From: Tommaso Merciai <[email protected]> > Sent: 26 May 2026 08:07 > Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas > RZ/G3L LVDS encoder > > Hi Biju, > Thanks for your patch. > > On Sun, May 24, 2026 at 08:44:50PM +0100, Biju wrote: > > From: Biju Das <[email protected]> > > > > Document the LVDS encoder IP found on the RZ/G3L SoC. It supports > > single-link mode. LVDS and the DSI interface share a peripheral clock > > and the MIPI_DSI_PRESET_N reset signal. However, the LVDS module > > cannot be used at the same time as MIPI-DSI. > > > > Same here, this should be v3 instead of v2. Will send this as v3. Cheers, Biju > Apart from that patch LGTM. > > Reviewed-by: Tommaso Merciai <[email protected]> > > Kind Regards, > Tommaso > > > Signed-off-by: Tommaso Merciai <[email protected]> > > Acked-by: Conor Dooley <[email protected]> > > Signed-off-by: Biju Das <[email protected]> > > --- > > v2->v3: > > * No change. > > v1->v2: > > * Collected tag. > > --- > > .../bridge/renesas,r9a08g046-lvds.yaml | 128 ++++++++++++++++++ > > 1 file changed, 128 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvd > > s.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-l > > vds.yaml > > b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-l > > vds.yaml > > new file mode 100644 > > index 000000000000..b1f6d020ae7b > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g0 > > +++ 46-lvds.yaml > > @@ -0,0 +1,128 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.y > > +aml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/G3L LVDS Encoder > > + > > +maintainers: > > + - Biju Das <[email protected]> > > + - Tommaso Merciai <[email protected]> > > + > > +description: | > > + This binding describe the LVDS encoder embedded in the Renesas > > +RZ/G3L > > + SoC. The encoder can operate in LVDS Single-link mode with 4 lanes > > + (Data) + 1 lane (Clock). > > + > > +properties: > > + compatible: > > + const: renesas,r9a08g046-lvds > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Peripheral clock > > + - description: PHY clock > > + - description: Dot clock > > + > > + clock-names: > > + items: > > + - const: pclk > > + - const: phyclk > > + - const: dotclk > > + > > + resets: > > + items: > > + - description: LVDS_RESET_N > > + - description: MIPI_DSI_PRESET_N > > + - description: MIPI_DSI_CMN_RSTB > > + - description: MIPI_DSI_ARESET_N > > + > > + reset-names: > > + items: > > + - const: lvdrst > > + - const: prst > > + - const: rst > > + - const: arst > > + > > + power-domains: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Input channel, directly connected to the Display Unit. > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: | > > + Output channel, directly connected to the LVDS panel or bridge. > > + > > + required: > > + - port@0 > > + - port@1 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - resets > > + - reset-names > > + - power-domains > > + - ports > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/renesas,r9a08g046-cpg.h> > > + > > + lvds-cmn@108a0000 { > > + compatible = "renesas,r9a08g046-lvds-cmn", > > + "simple-mfd", "syscon"; > > + reg = <0x108a0000 0x10000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + lvds0: lvds@10 { > > + compatible = "renesas,r9a08g046-lvds"; > > + reg = <0x10 0x8>; > > + clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>, > > + <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>, > > + <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>; > > + clock-names = "pclk", "phyclk", "dotclk"; > > + resets = <&cpg R9A08G046_LVDS_RESET_N>, > > + <&cpg R9A08G046_MIPI_DSI_PRESET_N>, > > + <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>, > > + <&cpg R9A08G046_MIPI_DSI_ARESET_N>; > > + reset-names = "lvdrst", "prst", "rst", "arst"; > > + power-domains = <&cpg>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + lvds0_in: endpoint { > > + remote-endpoint = <&du_out_lvds0>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + lvds0_out: endpoint { > > + remote-endpoint = <&panel_in>; > > + }; > > + }; > > + }; > > + }; > > + }; > > +... > > -- > > 2.43.0 > >
