On 5/27/26 14:14, Jason Gunthorpe wrote: > On Wed, May 27, 2026 at 08:55:49AM +0200, Christian König wrote: >> On 5/26/26 16:43, Zhiping Zhang wrote: >>> This series adds TLP Processing Hints (TPH) support to the VFIO dma-buf >>> export path, allowing importing drivers (e.g. mlx5) to use the >>> exporter's steering tag when performing peer-to-peer DMA into a >>> VFIO-owned device. >> >> I'm not an expert for TPH, but that sounds very strange to me. >> >> As far as I know the TLP Processing Hints allow devices to give a >> steering tag to the root complex together with memory accesses to >> give fine grained control about cache usage. In other words it is an >> extension to the classic snoop bit. > > TPHS includes an bit of data on every TLP and the data transits to the > eventual completer. > > It does not have to be a root port. > >> For P2P that is obviously nonsense because we don't have P2P support >> for cached accesses. > > For P2P the TPH data on the TLP will transit to the P2P completer > unchanged. > > It is up to the completer do define what it does with the TPH data. > > Typically root ports in CPUs will use TPH data for cache placement > instructions. But who knows what a P2P device will use it for. > > In Linux the driver that owns the completing address space gets to > specify how the TPH data works based on its own device specific > knowledge.
Yeah that's a good point, I should probably rephrase the question. I'm aware of how TPH works by adding the extra ST to the TLP. But my question is how is that useful to a PCIe endpoint? What is the effect of the ST here? I only know about the caching use case for the root complex and that's clearly not the case here. Regards, Christian. > > Jason
