Hi Sean,
On 5/29/2026 4:37 AM, Sean Paul wrote:
From: Sean Paul <[email protected]>
Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming
is active by clamping Segment 2 to the last user-provided LUT entry
value instead of hardcoding it to 1.0 (1 << 24).
Signed-off-by: Sean Paul <[email protected]>
Link:
https://lore.kernel.org/intel-gfx/[email protected]/ #v1
Link:
https://lore.kernel.org/intel-gfx/[email protected]/ #v2
We might need to trigger a CI run on intel-xe/intel-gfx since your
"poorly.run" e-mail id (unlike your google.com id) is not part of the
"allow-list".
Otherwise, with the assumption made in [1], LGTM
Reviewed-by: Chaitanya Kumar Borah <[email protected]>
[1]
https://lore.kernel.org/intel-gfx/dm4pr11mb636049ba2e517a22fb43a404f4...@dm4pr11mb6360.namprd11.prod.outlook.com/T/#t
Changes in v2:
- Split out into separate patches for pre/post csc fixes
- Dropped loop bounds fix in favor of [1]
Changes in v3:
- None
[1]- https://lore.kernel.org/r/[email protected]
---
drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 7ef870cd9a16..7185f3628dcf 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -4038,11 +4038,11 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
lut_val);
}
- /* Segment 2 */
+ /* Segment 2 - clamp to the last LUT value to prevent
step discontinuity */
do {
intel_de_write_dsb(display, dsb,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
- (1 << 24));
+ lut_val);
} while (i++ < 34);
} else {
/*TODO: Add for segment 0 */
