Hi Heiko,
On 6/3/2026 4:59 AM, Heiko Stuebner wrote:
> Am Dienstag, 24. März 2026, 09:58:37 Mitteleuropäische Sommerzeit schrieb
> Chaoyi Chen:
>> From: Chaoyi Chen <[email protected]>
>>
>> Different chips have varying support for the maximum bit rate per lane.
>>
>> Add calculation for the maximum per lane bit rate for various chip
>> platforms, and relax the bandwidth margin requirements.
>>
>> Signed-off-by: Chaoyi Chen <[email protected]>
>> ---
>> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 21 +++++++++++++++----
>> 1 file changed, 17 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
>> b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
>> index 3547d91b25d3..d3bacfae174e 100644
>> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
>> @@ -268,6 +268,7 @@ struct rockchip_dw_dsi_chip_data {
>>
>> unsigned int flags;
>> unsigned int max_data_lanes;
>> + unsigned long max_bit_rate_per_lane;
>> };
>>
>> struct dw_mipi_dsi_rockchip {
>> @@ -565,7 +566,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct
>> drm_display_mode *mode,
>> int bpp;
>> unsigned long mpclk, tmp;
>> unsigned int target_mbps = 1000;
>> - unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
>> + unsigned int max_mbps;
>> unsigned long best_freq = 0;
>> unsigned long fvco_min, fvco_max, fin, fout;
>> unsigned int min_prediv, max_prediv;
>> @@ -573,6 +574,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct
>> drm_display_mode *mode,
>> unsigned long _fbdiv, best_fbdiv;
>> unsigned long min_delta = ULONG_MAX;
>>
>> + max_mbps = dsi->cdata->max_bit_rate_per_lane;
>
> I may be blind, but how do the values come together?
> In the dppa_map table we have mbps values of 89 to 1500
> (MHz)
>
> While below the values set are
> .max_bit_rate_per_lane = 1500000000UL,
> in Hz I guess
>
> And I don't see the needed conversion somehow.
>
>
Oh! It should be:
max_mbps = dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC;
Will fix in v2.
>> dsi->format = format;
>> bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
>> if (bpp < 0) {
>> @@ -584,8 +586,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct
>> drm_display_mode *mode,
>>
>> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
>> if (mpclk) {
>> - /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
>> - tmp = mpclk * (bpp / lanes) * 10 / 8;
>> + /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
>> + tmp = mpclk * (bpp / lanes) * 10 / 9;
>
> Please do this in a separate patch, especially as I would expect some
> sort of explanation on why this is ok to do.
>
Sure! I'll split this out in the new series.
--
Best,
Chaoyi
