Hi Midgy, On 6/8/2026 5:05 AM, Midgy Balon wrote: > Hi Chaoyi, > >> As I said, it is v2. Could you please try using the code below instead and >> see if it works? >> [ auto_gate = read(RK_MMU_AUTO_GATING); auto_gate |= BIT(31); write(...) ] > > Thanks -- that's clearly the right shape (read-modify-write, before paging is > enabled, keeping the reset value instead of my clobbering 0x2). > > I rebuilt v7.1-rc6 (with the rocket RK3568 series + your per-device-ops work) > using your bit-31 version and tested it on a ROCK 3B: the NPU IOMMU comes up > and > services the NPU's DMA cleanly -- the NPU probes, attaches its domain, and > runs > repeated conv submissions with no DMA_READ_ERROR and no page-walk stall. No > regression from the write. > > To be precise about what I can and can't show: I tested both ways on v7.1-rc6 > -- > with your bit-31 write, and on the reset value (0x3) -- and the NPU > IOMMU services > the NPU's reads with zero faults in both cases (no DMA_READ_ERROR, no > page-walk > stall). So I don't have a failing baseline here that bit-31 visibly > fixes. Is the > AUTO_GATING write needed on current mainline, or only under conditions I'm not > reproducing (a particular traffic pattern / silicon rev)? I'll keep the patch > in > your form unless you'd prefer to drop it. > > One question so I document it correctly: what does bit 31 of > RK_MMU_AUTO_GATING > control on the v2 block -- is it a master "disable internal auto clock-gating" > for the page-table walker (i.e. so a TLB-miss walk's AXI master keeps its > clock > to completion)? The RK3568 TRM I have doesn't cover the IOMMU registers, so a > one-line description would let me write an accurate comment. >
Glad to hear this works. Please refer to the commit below. [0]: https://github.com/rockchip-linux/kernel/commit/7f8158fb41b5cc8e738aaeebc3637c50ebd74cae [1]: https://github.com/rockchip-linux/kernel/commit/6a355e5f9a2069a2309e240791bc3aad63b7324e -- Best, Chaoyi
