On 6/8/2026 4:02 PM, Krzysztof Kozlowski wrote:
On Mon, Jun 08, 2026 at 10:32:33AM +0800, Joey Lu wrote:
The existing schema hard-codes the five-clock/three-reset/dual-port
topology of the DC8200 IP block, preventing reuse for single-output
variants such as the Verisilicon DCUltraLite used in the Nuvoton MA35D1
SoC.
Rework the schema so that variant-specific constraints are expressed via
allOf/if blocks:
- Add nuvoton,ma35d1-dcu to the SoC-specific compatible enum. The
generic verisilicon,dc fallback remains the driver-binding string.
- Relax the top-level clocks/resets definitions to minItems ranges so
the base schema accepts both variants.
- Keep ports in the global required list and keep additionalProperties
tightened to unevaluatedProperties.
- Add an allOf/if block for thead,th1520-dc8200: five-clock (core, axi,
ahb, pix0, pix1), three-reset (core, axi, ahb).
- Add an allOf/if block for nuvoton,ma35d1-dcu: two-clock (core, pix0),
one-reset (core).
- Fix a stray space in the port@0 description.
- Add a DT example for the Nuvoton MA35D1 DCU Lite using ports/port@0.
Difference in clocks and resets does not need a new new example.
Best regards,
Krzysztof
Understood. I will remove the second example for nuvoton,ma35d1-dcu from
the binding.
