Synaptics VMM7100 DP-to-HDMI 2.1 protocol converters with branch firmware 7.1 (branch dev-ID "SYNAq", FW revision at DPCD 0x50a/0x50b) deterministically fail 8b/10b channel equalization when link training at the RBR link rate with 4 lanes. Clock recovery succeeds, but during channel equalization the device keeps toggling its requested voltage swing/pre-emphasis levels without ever converging, until the 5 attempt limit is reached. Only this link configuration fails. RBR with 1 or 2 lanes and all higher link rates with 2 or 4 lanes train reliably. A second dongle based on the same VMM7100 chip (same HW-rev 1.0) but with branch firmware 7.2 trains 4-lane RBR without issue, so this is a firmware problem in the converter, fixed by newer firmware. The failure was observed on PTL behind the board's non-transparent LTTPR, with the source granting all swing/pre-emphasis requests.
Add a quirk entry for these devices, so that drivers can avoid the RBR link rate for them. The quirk matching can't distinguish firmware revisions, so devices with fixed firmware are matched as well. Avoiding RBR is free for these PCONs, since any mode that fits into the RBR link bandwidth also fits into HBR, which they train reliably. The quirk will be handled by the i915 driver in a follow-up change. Cc: [email protected] Signed-off-by: Alexander Kaplan <[email protected]> --- drivers/gpu/drm/display/drm_dp_helper.c | 3 +++ include/drm/display/drm_dp_helper.h | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index 9c31e14cc413..a8737943ef11 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2558,6 +2558,9 @@ static const struct dpcd_quirk dpcd_quirk_list[] = { { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) }, { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) }, { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) }, + /* Synaptics VMM7100 DP-to-HDMI 2.1 PCONs fail channel EQ at the RBR link rate */ + { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 'q', '\0'), true, + BIT(DP_DPCD_QUIRK_NO_LINK_RATE_RBR) }, }; #undef OUI diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index 8c2d77a032f0..324197894300 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -863,6 +863,14 @@ enum drm_dp_quirk { * specific DSC pixel throughput. */ DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT, + /** + * @DP_DPCD_QUIRK_NO_LINK_RATE_RBR: + * + * The device fails 8b/10b channel equalization at the RBR link + * rate, but trains reliably at all higher link rates. Drivers + * should avoid the RBR link rate for these devices. + */ + DP_DPCD_QUIRK_NO_LINK_RATE_RBR, }; /** -- 2.54.0
