Extend the SDR plane color pipeline to include pre- and post-CSC 1D LUT blocks.
SDR planes use a smaller LUT size than HDR planes and therefore initialize the 1D LUT colorops with the appropriate hardware capacity. Signed-off-by: Chaitanya Kumar Borah <[email protected]> --- drivers/gpu/drm/i915/display/intel_color_pipeline.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c index 7457fa51cb97..136b9378ca48 100644 --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c @@ -15,6 +15,7 @@ #define MAX_COLOROP 4 #define PLANE_DEGAMMA_SIZE 128 #define PLANE_GAMMA_SIZE 32 +#define PLANE_DEGAMMA_SIZE_SDR 32 static const struct drm_colorop_funcs intel_colorop_funcs = { .destroy = intel_colorop_destroy, @@ -45,7 +46,9 @@ static const enum intel_color_block hdr_plane_pipeline[] = { static const enum intel_color_block sdr_plane_pipeline[] = { INTEL_PLANE_CB_YUV_RANGE_CORRECT, + INTEL_PLANE_CB_PRE_CSC_LUT, INTEL_PLANE_CB_CSC_FF, + INTEL_PLANE_CB_POST_CSC_LUT, }; static const u64 intel_plane_supported_csc_ff = @@ -68,8 +71,10 @@ struct intel_colorop *intel_color_pipeline_plane_add_colorop(struct drm_plane *p enum intel_color_block id) { struct drm_device *dev = plane->dev; + struct intel_display *display = to_intel_display(dev); struct intel_colorop *colorop; int ret; + bool is_hdr = icl_is_hdr_plane(display, to_intel_plane(plane)->id); colorop = intel_colorop_create(id); @@ -81,7 +86,9 @@ struct intel_colorop *intel_color_pipeline_plane_add_colorop(struct drm_plane *p ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane, &intel_colorop_funcs, - PLANE_DEGAMMA_SIZE, + is_hdr ? + PLANE_DEGAMMA_SIZE : + PLANE_DEGAMMA_SIZE_SDR, DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR, DRM_COLOROP_FLAG_ALLOW_BYPASS); break; -- 2.25.1
