[PATCH] drm/amd/display: avoid 64-bit division

[Arnd Bergmann]

From: Arnd Bergmann <a...@arndb.de>

64-bit division is costly on 32-bit targets and should be avoided:

x86_64-linux-ld: drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.o: in 
function `get_dp_dto_frequency_100hz':
dce_clock_source.c:(.text+0x407): undefined reference to `__udivdi3'
x86_64-linux-ld: drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.o: in 
function `dcn401_get_dp_dto_frequency_100hz':
dce_clock_source.c:(.text+0x8b8): undefined reference to `__udivdi3'

Replace the open-coded division with a div_u64() call where necessary.
This could be done in a more clever way using mul_u64_u32_shr()
or similar, but since this is called rarely, use the most readable
variant that works.

Fixes: 6f6483dbfacd ("drm/amd/display: Update get_pixel_clk_frequency() for 
DCN4x DCCG DP DTO")
Signed-off-by: Arnd Bergmann <a...@arndb.de>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 7c293917e6fd..501ab1a3bac2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1229,9 +1229,9 @@ static bool get_dp_dto_frequency_100hz(
                         */
                        modulo_hz = REG_READ(MODULO[inst]);
                        if (modulo_hz) {
-                               temp = div_u64((uint64_t)clock_hz * 
dp_dto_ref_khz * 10, modulo_hz);
-                               ASSERT(temp / 100 <= 0xFFFFFFFFUL);
-                               *pixel_clk_100hz = (unsigned int)(temp / 100);
+                               temp = clock_hz * dp_dto_ref_khz * 10;
+                               ASSERT(temp <= INT_MAX * modulo_hz * 100);
+                               *pixel_clk_100hz = div_u64(temp, modulo_hz * 
100);
                        } else
                                *pixel_clk_100hz = 0;
                } else {
@@ -1286,12 +1286,12 @@ static bool dcn401_get_dp_dto_frequency_100hz(const 
struct clock_source *clock_s
                 */
                temp = (unsigned long long)dp_dto_integer * modulo_hz + 
phase_hz;
 
-               if (temp / 100 > 0xFFFFFFFFUL) {
+               if (temp > (UINT_MAX * 100ULL)) {
                        /* pixel rate 100hz should never be this high, if it 
is, throw an assert and return 0  */
                        BREAK_TO_DEBUGGER();
                        *pixel_clk_100hz = 0;
                } else {
-                       *pixel_clk_100hz = (unsigned int)(temp / 100);
+                       *pixel_clk_100hz = div_u64(temp, 100);
                }
 
                return true;
-- 
2.39.5