On Fri, Jun 19, 2026 at 11:10:16AM +0100, Biju wrote: > From: Biju Das <[email protected]> > > Document the LVDS encoder IP found on the RZ/G3L SoC. It supports > single-link mode. LVDS and the DSI interface share a peripheral clock and > the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be > used at the same time as MIPI-DSI. > > Signed-off-by: Tommaso Merciai <[email protected]> > Signed-off-by: Biju Das <[email protected]> > ---
Reviewed-by: Krzysztof Kozlowski <[email protected]> Best regards, Krzysztof
