From: Pedro Yudi Honda <[email protected]> In riscv.rs, replave the following `transmute` traits with their `zerocopy` equivalents:
- `transmute::FromBytes` -> `zerocopy::FromBytes` Update call sites accordingly. Signed-off-by: Pedro Yudi Honda <[email protected]> --- drivers/gpu/nova-core/firmware/riscv.rs | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-core/firmware/riscv.rs index 2afa7f36404e..ba56bc7d4188 100644 --- a/drivers/gpu/nova-core/firmware/riscv.rs +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -7,8 +7,7 @@ device, dma::Coherent, firmware::Firmware, - prelude::*, - transmute::FromBytes, // + prelude::*, // }; use crate::{ @@ -18,7 +17,7 @@ /// Descriptor for microcode running on a RISC-V core. #[repr(C)] -#[derive(Debug)] +#[derive(Debug, FromBytes)] struct RmRiscvUCodeDesc { version: u32, bootloader_offset: u32, @@ -36,9 +35,6 @@ struct RmRiscvUCodeDesc { monitor_code_size: u32, } -// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability. -unsafe impl FromBytes for RmRiscvUCodeDesc {} - impl RmRiscvUCodeDesc { /// Interprets the header of `bin_fw` as a [`RmRiscvUCodeDesc`] and returns it. /// @@ -50,7 +46,7 @@ fn new(bin_fw: &BinFirmware<'_>) -> Result<Self> { bin_fw .fw .get(offset..end) - .and_then(Self::from_bytes_copy) + .and_then(|b| Self::read_from_bytes(b).ok()) .ok_or(EINVAL) } } -- 2.34.1
