From: Bibek Kumar Patro <[email protected]> Add the Adreno GPU IOMMU (adreno_smmu) node for the Shikra SoC.
Signed-off-by: Bibek Kumar Patro <[email protected]> Signed-off-by: Imran Shaik <[email protected]> Signed-off-by: Komal Bajaj <[email protected]> Signed-off-by: Akhil P Oommen <[email protected]> --- arch/arm64/boot/dts/qcom/shikra.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 1ccb0f1419aa..398cb1a4dc86 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -655,6 +655,35 @@ gpucc: clock-controller@5990000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@59a0000 { + compatible = "qcom,shikra-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x059a0000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + dispcc: clock-controller@5f00000 { compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc"; reg = <0x0 0x05f00000 0x0 0x20000>; -- 2.51.0
