In preparation for adding support for the eDP PHY found in newer SoCs, transfer the register mask for PHYD_TX_LN_EN to SoC specific data.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]> --- drivers/phy/mediatek/phy-mtk-dp.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c index 73fc724e0ecc..2c402b416683 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -214,6 +214,7 @@ struct mtk_dp_phya_imp_sel { * @regs_ana_lane: Register (layout) offsets for ana_lan * @regs_dig_glb: Register (layout) offsets for dig_glb * @regs_dig_lane: Register (layout) offsets for dig_lan + * @mask_dig_tx_ln: Register mask for PHYD_TX_LN_EN field * @val_dig_bitrate:IP Version specific register values for Bit Rate setting * @ana_bias_r: Internal resistance "R" Selection Settings (global) * @ana_cktx_imp: TX Clock Impedance Selection Settings (global) @@ -233,6 +234,9 @@ struct mtk_dp_phy_pdata { const u8 *regs_dig_glb; const u8 *regs_dig_lane; + /* Register masks */ + u32 mask_dig_tx_ln; + /* IP-Version specific register value arrays */ const u8 *val_dig_bitrate; @@ -370,10 +374,10 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) val = 0; for (i = 0; i < opts->dp.lanes; i++) - val |= FIELD_PREP(PHYD_TX_LN_EN, BIT(i)); + val |= field_prep(pdata->mask_dig_tx_ln, BIT(i)); regmap_update_bits(dp_phy->regmap, pdata->off_dig_glb + reg_dig_tx_ctl, - PHYD_TX_LN_EN, val); + pdata->mask_dig_tx_ln, val); } if (opts->dp.set_voltages) { @@ -442,7 +446,7 @@ static int mtk_dp_phy_disable_all_lanes(struct mtk_dp_phy *dp_phy) return ret; /* Get mask of currently enabled lane */ - val = FIELD_GET(PHYD_TX_LN_EN, val); + val = field_get(pdata->mask_dig_tx_ln, val); /* Disable all lanes (needs to be done one by one, from last to first) */ do { @@ -451,7 +455,7 @@ static int mtk_dp_phy_disable_all_lanes(struct mtk_dp_phy *dp_phy) ret = regmap_clear_bits(dp_phy->regmap, pdata->off_dig_glb + regs[DP_PHYD_TX_CTL_0], - FIELD_PREP(PHYD_TX_LN_EN, lane_num)); + field_prep(pdata->mask_dig_tx_ln, lane_num)); if (ret) return ret; } while (val); @@ -726,6 +730,7 @@ static const struct mtk_dp_phy_pdata mt8195_dp_phy_data = { .regs_ana_lane = mt8195_phy_ana_lane_regs, .regs_dig_glb = mt8195_phy_dig_glb_regs, .regs_dig_lane = mt8195_phy_dig_lane_regs, + .mask_dig_tx_ln = PHYD_TX_LN_EN, .val_dig_bitrate = mt8195_phy_dig_bitrate_val, .ana_bias_r = 15, .ana_cktx_imp = 8, -- 2.54.0
