Since mediatek-drm shifted from hardcoded per-SoC-per-Board path definitions for the display controller to devicetree graph based path building, the first ones are used less and less, and those are also decreasing ease of code browsability (hence, readability) in the mtk_drm_drv.c file.
This means that those big arrays are almost irrelevant now (for modern code, of course). Seen the need to keep compatibility with older devicetrees, then, move all of the deprecated arrays in new mtk_drm_legacy files and add a big warning to those, explaining that no new SoCs must be implemented like so, and making it clear that it shall exclusively contain legacy and deprecated code. Also, especially with the restructuring work that is currently in progress (with MuteX finally getting trigger-sources support and other changes that will follow), it is expected to see more code being moved in the mtk_drm_legacy territory. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 277 +------------------ drivers/gpu/drm/mediatek/mtk_drm_legacy.c | 309 ++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_legacy.h | 28 ++ 4 files changed, 339 insertions(+), 276 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_legacy.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_legacy.h diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 8079962597c8..f40ad5565716 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -13,6 +13,7 @@ mediatek-drm-y := mtk_crtc.o \ mtk_disp_rdma.o \ mtk_disp_wdma.o \ mtk_drm_drv.o \ + mtk_drm_legacy.o \ mtk_dsi.o \ mtk_dpi.o \ mtk_ethdr.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 09c7d038348d..1396cbc65627 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -35,6 +35,7 @@ #include "mtk_ddp_comp.h" #include "mtk_disp_drv.h" #include "mtk_drm_drv.h" +#include "mtk_drm_legacy.h" #define DRIVER_NAME "mediatek" #define DRIVER_DESC "Mediatek SoC DRM" @@ -63,282 +64,6 @@ static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { .atomic_commit = drm_atomic_helper_commit, }; -static const struct mtk_drm_comp_definition mt2701_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_BLS }, - { DDP_COMPONENT_DSI0 }, -}; - -static const struct mtk_drm_comp_definition mt2701_mtk_ddp_ext[] = { - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt2701_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt2701_mtk_ddp_main, - .len = ARRAY_SIZE(mt2701_mtk_ddp_main), - }, - [CRTC_EXT] = { - .comp = mt2701_mtk_ddp_ext, - .len = ARRAY_SIZE(mt2701_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt2712_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_OD0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_DPI0 }, - { DDP_COMPONENT_PWM0 }, -}; - -static const struct mtk_drm_comp_definition mt2712_mtk_ddp_ext[] = { - { DDP_COMPONENT_OVL1 }, - { DDP_COMPONENT_COLOR1 }, - { DDP_COMPONENT_AAL1 }, - { DDP_COMPONENT_OD1 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI1 }, - { DDP_COMPONENT_PWM1 }, -}; - -static const struct mtk_drm_comp_definition mt2712_mtk_ddp_third[] = { - { DDP_COMPONENT_RDMA2 }, - { DDP_COMPONENT_DSI3 }, - { DDP_COMPONENT_PWM2 }, -}; - -struct mtk_drm_path_definition mt2712_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt2712_mtk_ddp_main, - .len = ARRAY_SIZE(mt2712_mtk_ddp_main), - }, - [CRTC_EXT] = { - .comp = mt2712_mtk_ddp_ext, - .len = ARRAY_SIZE(mt2712_mtk_ddp_ext), - }, - [CRTC_THIRD] = { - .comp = mt2712_mtk_ddp_third, - .len = ARRAY_SIZE(mt2712_mtk_ddp_third), - }, -}; - -static const struct mtk_drm_comp_definition mt7623_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_BLS }, - { DDP_COMPONENT_DPI0 }, -}; - -static const struct mtk_drm_comp_definition mt7623_mtk_ddp_ext[] = { - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DSI0 }, -}; - -struct mtk_drm_path_definition mt7623_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt7623_mtk_ddp_main, - .len = ARRAY_SIZE(mt7623_mtk_ddp_main), - }, - [CRTC_EXT] = { - .comp = mt7623_mtk_ddp_ext, - .len = ARRAY_SIZE(mt7623_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8167_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_DSI0 }, -}; - -struct mtk_drm_path_definition mt8167_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt8167_mtk_ddp_main, - .len = ARRAY_SIZE(mt8167_mtk_ddp_main), - }, -}; - -static const struct mtk_drm_comp_definition mt8173_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_OD0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_UFOE }, - { DDP_COMPONENT_DSI0 }, - { DDP_COMPONENT_PWM0 }, -}; - -static const struct mtk_drm_comp_definition mt8173_mtk_ddp_ext[] = { - { DDP_COMPONENT_OVL1 }, - { DDP_COMPONENT_COLOR1 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt8173_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt8173_mtk_ddp_main, - .len = ARRAY_SIZE(mt8173_mtk_ddp_main), - }, - [CRTC_EXT] = { - .comp = mt8173_mtk_ddp_ext, - .len = ARRAY_SIZE(mt8173_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8183_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, -}; - -static const struct mtk_drm_comp_definition mt8183_mtk_ddp_ext[] = { - { DDP_COMPONENT_OVL_2L1 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt8183_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt8183_mtk_ddp_main, - .len = ARRAY_SIZE(mt8183_mtk_ddp_main), - }, - [CRTC_EXT] = { - .comp = mt8183_mtk_ddp_ext, - .len = ARRAY_SIZE(mt8183_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8186_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, -}; - -static const struct mtk_drm_comp_definition mt8186_mtk_ddp_ext[] = { - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt8186_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt8186_mtk_ddp_main, - .len = ARRAY_SIZE(mt8186_mtk_ddp_main), - }, - [CRTC_EXT] = { - .comp = mt8186_mtk_ddp_ext, - .len = ARRAY_SIZE(mt8186_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8188_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, -}; - -struct mtk_drm_path_definition mt8188_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt8188_mtk_ddp_main, - .len = ARRAY_SIZE(mt8188_mtk_ddp_main), - }, -}; - -static const struct mtk_drm_comp_definition mt8192_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, -}; - -static const struct mtk_drm_comp_definition mt8192_mtk_ddp_ext[] = { - { DDP_COMPONENT_OVL_2L2 }, - { DDP_COMPONENT_RDMA4 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt8192_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt8192_mtk_ddp_main, - .len = ARRAY_SIZE(mt8192_mtk_ddp_main), - }, - [CRTC_EXT] = { - .comp = mt8192_mtk_ddp_ext, - .len = ARRAY_SIZE(mt8192_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8195_mtk_ddp_main[] = { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSC0 }, - { DDP_COMPONENT_MERGE0 }, - { DDP_COMPONENT_DP_INTF0 }, -}; - -static const struct mtk_drm_comp_definition mt8195_mtk_ddp_ext[] = { - { DDP_COMPONENT_DRM_OVL_ADAPTOR }, - { DDP_COMPONENT_MERGE5 }, - { DDP_COMPONENT_DP_INTF1 }, -}; - -struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[MAX_CRTC] = { - [CRTC_MAIN] = { - .comp = mt8195_mtk_ddp_main, - .len = ARRAY_SIZE(mt8195_mtk_ddp_main), - }, -}; - -struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[MAX_CRTC] = { - [CRTC_EXT] = { - .comp = mt8195_mtk_ddp_ext, - .len = ARRAY_SIZE(mt8195_mtk_ddp_ext), - }, -}; - static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .output_paths = mt2701_legacy_paths, .shadow_register = true, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.c b/drivers/gpu/drm/mediatek/mtk_drm_legacy.c new file mode 100644 index 000000000000..623e510de9ff --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Compatibility layer for legacy mediatek-drm + * + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno <[email protected]> + * + * All (or most of) MediaTek SoCs released since around year 2014 onwards + * have got a new Multimedia System (and Display Controller) architecture, + * featuring an extreme flexibility on the connection of all of the various + * multimedia-related hardware components (or sub-IPs). + * + * Many different boards based on those SoCs are using different displays, + * different outputs, hence wildly different display pipelines: for this, + * a solution based on a devicetree graph (OF Graph) was chosen for setting + * up the correct pipeline for each device. + * + * However, removing the hardcoded display controller paths would break all + * of the devices using the new display driver on an old devicetree. + * + * This compatibility layer makes possible to keep the display controller + * functionality working when a board/device: + * - Uses an old devicetree with no OF Graph; and + * - Uses a new kernel with the new mediatek-drm graph-based pipeline + * building code. + * + * ** WARNING ** + * This exists only to avoid ABI breakages and no new SoC should ever be + * added to this file. + */ + +#include "mtk_drm_drv.h" +#include "mtk_drm_legacy.h" + +static const struct mtk_drm_comp_definition mt2701_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_BLS }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt2701_mtk_ddp_ext[] = { + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt2701_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt2701_mtk_ddp_main, + .len = ARRAY_SIZE(mt2701_mtk_ddp_main), + }, + [CRTC_EXT] = { + .comp = mt2701_mtk_ddp_ext, + .len = ARRAY_SIZE(mt2701_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_OD0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_DPI0 }, + { DDP_COMPONENT_PWM0 }, +}; + +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_ext[] = { + { DDP_COMPONENT_OVL1 }, + { DDP_COMPONENT_COLOR1 }, + { DDP_COMPONENT_AAL1 }, + { DDP_COMPONENT_OD1 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI1 }, + { DDP_COMPONENT_PWM1 }, +}; + +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_third[] = { + { DDP_COMPONENT_RDMA2 }, + { DDP_COMPONENT_DSI3 }, + { DDP_COMPONENT_PWM2 }, +}; + +struct mtk_drm_path_definition mt2712_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt2712_mtk_ddp_main, + .len = ARRAY_SIZE(mt2712_mtk_ddp_main), + }, + [CRTC_EXT] = { + .comp = mt2712_mtk_ddp_ext, + .len = ARRAY_SIZE(mt2712_mtk_ddp_ext), + }, + [CRTC_THIRD] = { + .comp = mt2712_mtk_ddp_third, + .len = ARRAY_SIZE(mt2712_mtk_ddp_third), + }, +}; + +static const struct mtk_drm_comp_definition mt7623_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_BLS }, + { DDP_COMPONENT_DPI0 }, +}; + +static const struct mtk_drm_comp_definition mt7623_mtk_ddp_ext[] = { + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DSI0 }, +}; + +struct mtk_drm_path_definition mt7623_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt7623_mtk_ddp_main, + .len = ARRAY_SIZE(mt7623_mtk_ddp_main), + }, + [CRTC_EXT] = { + .comp = mt7623_mtk_ddp_ext, + .len = ARRAY_SIZE(mt7623_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8167_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_DSI0 }, +}; + +struct mtk_drm_path_definition mt8167_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt8167_mtk_ddp_main, + .len = ARRAY_SIZE(mt8167_mtk_ddp_main), + }, +}; + +static const struct mtk_drm_comp_definition mt8173_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_OD0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_UFOE }, + { DDP_COMPONENT_DSI0 }, + { DDP_COMPONENT_PWM0 }, +}; + +static const struct mtk_drm_comp_definition mt8173_mtk_ddp_ext[] = { + { DDP_COMPONENT_OVL1 }, + { DDP_COMPONENT_COLOR1 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8173_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt8173_mtk_ddp_main, + .len = ARRAY_SIZE(mt8173_mtk_ddp_main), + }, + [CRTC_EXT] = { + .comp = mt8173_mtk_ddp_ext, + .len = ARRAY_SIZE(mt8173_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8183_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt8183_mtk_ddp_ext[] = { + { DDP_COMPONENT_OVL_2L1 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8183_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt8183_mtk_ddp_main, + .len = ARRAY_SIZE(mt8183_mtk_ddp_main), + }, + [CRTC_EXT] = { + .comp = mt8183_mtk_ddp_ext, + .len = ARRAY_SIZE(mt8183_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8186_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt8186_mtk_ddp_ext[] = { + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8186_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt8186_mtk_ddp_main, + .len = ARRAY_SIZE(mt8186_mtk_ddp_main), + }, + [CRTC_EXT] = { + .comp = mt8186_mtk_ddp_ext, + .len = ARRAY_SIZE(mt8186_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8188_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, +}; + +struct mtk_drm_path_definition mt8188_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt8188_mtk_ddp_main, + .len = ARRAY_SIZE(mt8188_mtk_ddp_main), + }, +}; + +static const struct mtk_drm_comp_definition mt8192_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt8192_mtk_ddp_ext[] = { + { DDP_COMPONENT_OVL_2L2 }, + { DDP_COMPONENT_RDMA4 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8192_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt8192_mtk_ddp_main, + .len = ARRAY_SIZE(mt8192_mtk_ddp_main), + }, + [CRTC_EXT] = { + .comp = mt8192_mtk_ddp_ext, + .len = ARRAY_SIZE(mt8192_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8195_mtk_ddp_main[] = { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSC0 }, + { DDP_COMPONENT_MERGE0 }, + { DDP_COMPONENT_DP_INTF0 }, +}; + +static const struct mtk_drm_comp_definition mt8195_mtk_ddp_ext[] = { + { DDP_COMPONENT_DRM_OVL_ADAPTOR }, + { DDP_COMPONENT_MERGE5 }, + { DDP_COMPONENT_DP_INTF1 }, +}; + +struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[MAX_CRTC] = { + [CRTC_MAIN] = { + .comp = mt8195_mtk_ddp_main, + .len = ARRAY_SIZE(mt8195_mtk_ddp_main), + }, +}; + +struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[MAX_CRTC] = { + [CRTC_EXT] = { + .comp = mt8195_mtk_ddp_ext, + .len = ARRAY_SIZE(mt8195_mtk_ddp_ext), + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.h b/drivers/gpu/drm/mediatek/mtk_drm_legacy.h new file mode 100644 index 000000000000..a87741ec0dcd --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Support for legacy mediatek-drm display paths + * + * Please read mtk_drm_legacy.c for more information. + * + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno <[email protected]> + */ + +#ifndef MTK_DRM_LEGACY_H +#define MTK_DRM_LEGACY_H + +struct mtk_drm_path_definition; + +extern struct mtk_drm_path_definition mt2701_legacy_paths[]; +extern struct mtk_drm_path_definition mt2712_legacy_paths[]; +extern struct mtk_drm_path_definition mt7623_legacy_paths[]; +extern struct mtk_drm_path_definition mt8167_legacy_paths[]; +extern struct mtk_drm_path_definition mt8173_legacy_paths[]; +extern struct mtk_drm_path_definition mt8183_legacy_paths[]; +extern struct mtk_drm_path_definition mt8186_legacy_paths[]; +extern struct mtk_drm_path_definition mt8188_legacy_paths[]; +extern struct mtk_drm_path_definition mt8192_legacy_paths[]; +extern struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[]; +extern struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[]; + +#endif /* MTK_DRM_LEGACY_H */ -- 2.54.0
