The resources (channels, syncpoints) provided by Host1x can be split into multiple independent partitions similar to e.g. PCIe VFs, which can be assigned to virtual machines, non-CPU embedded controllers, or other bus masters.
Each partition has its own MMIO register region and interrupts through which the set of channels and syncpoints assigned to it can be accessed. This set is configured via the hypervisor MMIO region earlier during boot. This series adds device tree bindings and support in the driver to function when Host1x has been partitioned in this way, by making the driver work without access to the hypervisor region and with a limited set of channels and syncpoints. Signed-off-by: Mikko Perttunen <[email protected]> --- Changes in v2: - Updated commit messages to clarify software view of registers - Minor rewording of schema description for channels/syncpoints properties - Rebased on v7.2-rc1 - Link to v1: https://patch.msgid.link/[email protected] --- Mikko Perttunen (4): dt-bindings: display: tegra: Make non-vm registers optional dt-bindings: display: tegra: Add channel/syncpoint range properties gpu: host1x: Support running without hv/common registers gpu: host1x: Allow limiting usable channel and syncpoint ranges .../display/tegra/nvidia,tegra20-host1x.yaml | 52 ++++++++++++++++------ drivers/gpu/host1x/channel.c | 6 +-- drivers/gpu/host1x/dev.c | 52 +++++++++++++++++++--- drivers/gpu/host1x/dev.h | 3 ++ drivers/gpu/host1x/hw/cdma_hw.c | 3 ++ drivers/gpu/host1x/hw/debug_hw_1x06.c | 3 ++ drivers/gpu/host1x/syncpt.c | 21 +++++---- 7 files changed, 110 insertions(+), 30 deletions(-) --- base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482 change-id: 20250919-host1x-nohv-071ed7c6ac4f
