On Tue, 23 Jun 2026 10:35:06 +0800, Damon Ding wrote:
> VS/PE values returned by drm_dp_get_adjust_request_voltage() and
> drm_dp_get_adjust_request_pre_emphasis() are already encoded to their
> native DPCD register bit positions. However, DPCD_VOLTAGE_SWING_SET /
> DPCD_PRE_EMPHASIS_SET macros perform an extra internal shift. Feeding
> the raw offset-bearing values directly leads to overlapping bitfields
> and invalid lane training configuration, causing link training failures
> and black screen.
>
> [...]
Applied, thanks!
[1/1] drm/bridge: analogix_dp: Fix PE/VS value shift mismatch during link
training
commit: 6bb8898f702385d363dc2c513a1efa62807f8068
Best regards,
--
Heiko Stuebner <[email protected]>
