On 7/6/2026 2:29 PM, Konrad Dybcio wrote: > On 7/5/26 10:14 AM, Akhil P Oommen wrote: >> From: Puranam V G Tejaswi <[email protected]> >> >> Add support for Adreno A722, a member of the GEN1 A7xx family. It is >> derived from A730 and shares the same IP-level configurations: HWCG >> registers, protected registers, GBIF CX registers and gmu_cgc_mode. >> Major differences include lower cache/core counts, 1MB GMEM, no >> Concurrent Binning & LPAC support. Some of the peripheral blocks like >> RSCC are from A740 that resulted in updates to RSC layout. >> >> Add a new entry to the catalog to describe the usual configuration and >> few additional fixup mainly due to missing CB/LPAC features and updated >> RSC layout. >> >> Signed-off-by: Puranam V G Tejaswi <[email protected]> >> Signed-off-by: Akhil P Oommen <[email protected]> >> --- > > [...] > >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -710,7 +710,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) >> gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); >> gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); >> gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, >> - adreno_is_a740_family(adreno_gpu) ? 0x80000021 : >> 0x80000000); >> + (adreno_is_a740_family(adreno_gpu) || >> + adreno_is_a722(adreno_gpu)) ? 0x80000021 : 0x80000000); > > This is a discrepancy vs kgsl (did you look at gen7_14 instead of > gen7_17? did you test this on device?)
Both 7_17 and 7_14 are same GPU IP. Yes, this was tested on Eliza MTP. > > [...] > >> /* The second spin of A7xx GPUs messed with some register offsets.. */ >> - if (adreno_is_a740_family(adreno_gpu)) >> + if (adreno_is_a740_family(adreno_gpu) || adreno_is_a722(adreno_gpu)) >> seqmem0_drv0_reg = REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740; > > Likewise > > [...] > >> /* The second spin of A7xx GPUs messed with some register offsets.. */ >> - if (adreno_is_a740_family(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) >> + if (adreno_is_a740_family(adreno_gpu) || adreno_is_a722(adreno_gpu) || >> + adreno_is_a8xx(adreno_gpu)) >> seqmem_off = 4; > > Likewise > >> >> /* Make sure there are no outstanding RPMh votes */ >> @@ -1100,7 +1104,8 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) >> gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, >> val, (val & 1), 100, 1000); >> >> - if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a8xx(adreno_gpu)) >> + if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a722(adreno_gpu) && >> + !adreno_is_a8xx(adreno_gpu)) >> return; > > Likewise > > You also need to if-out concurrent binning for this SKU You mean the PM4 pkts? If yes, fw will skip them as NOP. -Akhil. > > Konrad
