On 7/6/2026 3:07 PM, Konrad Dybcio wrote: > On 7/5/26 10:00 AM, Akhil P Oommen wrote: >> Adreno 840 present in Kaanapali SoC is the second generation GPU in >> A8x family. It is based on the new slice architecture with 3 slices, >> higher GMEM/caches etc. >> >> There is some re-arrangement in the reglist to properly cover maximum >> register region. Other than this, the DT description is mostly similar >> to the existing chipsets except the OPP tables. >> >> Reviewed-by: Dmitry Baryshkov <[email protected]> >> Signed-off-by: Akhil P Oommen <[email protected]> >> --- > > [...] > >> + qcom,gmu = <&gmu>; >> + #cooling-cells = <2>; >> + >> + nvmem-cells = <&gpu_speed_bin>; >> + nvmem-cell-names = "speed_bin"; > > This looks good to me, but I thought that on a8x, we're supposed to use > the freq limiting register in CX_MISC - is either of them preferred? > Or are they just hardwired to the same thing by chance
I believe the other register would work, but I don't have a fused hw to test. OTOH, this is what is commercialized. Btw, the CX_MISC register is not present in all A8x GPUs, for eg: Pakala. -Akhil. > > Konrad
