msm_dp_ctrl_on_stream() enables the stream pixel clock before waiting for
video readiness. If that wait times out, it returns without disabling the
clock or clearing stream_clks_on.
Route the timeout path through cleanup and disable the clock only if this
call enabled it.
Fixes: 9bd0946d5ca1 ("drm/msm/dp: simplify stream clocks handling")
Signed-off-by: Yuho Choi <[email protected]>
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 86ef8c89ad44..139e9fa25d6a 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -2469,6 +2469,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl
*msm_dp_ctrl, bool force_link_train
{
int ret = 0;
bool mainlink_ready = false;
+ bool stream_clk_enabled = false;
struct msm_dp_ctrl_private *ctrl;
unsigned long pixel_rate;
unsigned long pixel_rate_orig;
@@ -2514,6 +2515,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl
*msm_dp_ctrl, bool force_link_train
goto end;
}
ctrl->stream_clks_on = true;
+ stream_clk_enabled = true;
}
if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl))
@@ -2543,13 +2545,17 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl
*msm_dp_ctrl, bool force_link_train
ret = msm_dp_ctrl_wait4video_ready(ctrl);
if (ret)
- return ret;
+ goto end;
mainlink_ready = msm_dp_ctrl_mainlink_ready(ctrl);
drm_dbg_dp(ctrl->drm_dev,
"mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
end:
+ if (stream_clk_enabled && ret) {
+ clk_disable_unprepare(ctrl->pixel_clk);
+ ctrl->stream_clks_on = false;
+ }
return ret;
}
--
2.43.0
