> -----Original Message----- > From: Intel-xe <[email protected]> On Behalf Of Chaitanya > Kumar Borah > Sent: Wednesday, June 17, 2026 2:38 PM > To: [email protected]; [email protected]; intel- > [email protected] > Cc: Borah, Chaitanya Kumar <[email protected]> > Subject: [v3 07/14] drm/i915/color: Add YCbCr limited-to-full range color > block > support > > Add support for color block which performs YCbCr limited-to-full range > expansion > in the plane color pipeline. The color block is represented using > DRM_COLOROP_FIXED_MATRIX colorop. > > v2: > - s/yuv_range_correct/yuv_range_correction_disable/ to mirror > HW register bit naming > - Fix inverted bypass logic: assign bypass state directly since > bypass=true means HW range correction should be disabled Changes Look Good to me. Reviewed-by: Uma Shankar <[email protected]> > Assisted-by: Claude:claude-opus-4.6 > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_color_pipeline.c | 6 ++++++ > drivers/gpu/drm/i915/display/intel_display_limits.h | 1 + > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_plane.c | 3 +++ > drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 ++ > 5 files changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c > b/drivers/gpu/drm/i915/display/intel_color_pipeline.c > index 2ef42a133a98..7d25f4fbfa9b 100644 > --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c > +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c > @@ -108,6 +108,12 @@ struct intel_colorop > *intel_color_pipeline_plane_add_colorop(struct drm_plane *p > > intel_plane_supported_csc_ff, > > DRM_COLOROP_FLAG_ALLOW_BYPASS); > break; > + case INTEL_PLANE_CB_YUV_RANGE_CORRECT: > + ret = drm_plane_colorop_fixed_matrix_init(dev, &colorop->base, > plane, > + &intel_colorop_funcs, > + > BIT(DRM_COLOROP_FM_YCBCR_LIMITED_FULL), > + > DRM_COLOROP_FLAG_ALLOW_BYPASS); > + break; > default: > drm_err(plane->dev, "Invalid colorop id [%d]", id); > ret = -EINVAL; > diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h > b/drivers/gpu/drm/i915/display/intel_display_limits.h > index 7ba7360c574e..9493d333a242 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_limits.h > +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h > @@ -172,6 +172,7 @@ enum intel_color_block { > INTEL_PLANE_CB_CSC_FF, > INTEL_PLANE_CB_POST_CSC_LUT, > INTEL_PLANE_CB_3DLUT, > + INTEL_PLANE_CB_YUV_RANGE_CORRECT, > > INTEL_CB_MAX > }; > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 1b5a3c84a7f3..bc85d3c88706 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -683,6 +683,7 @@ struct intel_plane_state { > struct drm_property_blob *ctm, *degamma_lut, *gamma_lut, > *lut_3d; > enum drm_colorop_fixed_matrix_type csc_ff_type; /* For SDR > plane */ > bool csc_ff_enable; > + bool yuv_range_correction_disable; > } hw; > > struct i915_vma *ggtt_vma; > diff --git a/drivers/gpu/drm/i915/display/intel_plane.c > b/drivers/gpu/drm/i915/display/intel_plane.c > index 78ee3c357d8a..e2b496bd6266 100644 > --- a/drivers/gpu/drm/i915/display/intel_plane.c > +++ b/drivers/gpu/drm/i915/display/intel_plane.c > @@ -436,6 +436,9 @@ intel_plane_color_copy_uapi_to_hw_state(struct > intel_atomic_state *state, > !new_colorop_state->bypass; > plane_state->hw.csc_ff_type = > new_colorop_state- > >fixed_matrix_type; > + } else if (intel_colorop->id == > INTEL_PLANE_CB_YUV_RANGE_CORRECT) { > + plane_state- > >hw.yuv_range_correction_disable = > + new_colorop_state->bypass; > } else { > blob = new_colorop_state->bypass ? > NULL : new_colorop_state->data; > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 0e951b36ccca..9f4bc5a61ffb 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -1296,6 +1296,8 @@ static u32 glk_plane_color_ctl_input_csc(const struct > intel_plane_state *plane_s > } else if (!icl_is_hdr_plane(display, plane->id)) { > if (plane_state->hw.csc_ff_enable) > ctl |= intel_csc_ff_type_to_csc_mode(plane_state- > >hw.csc_ff_type); > + if (plane_state->hw.yuv_range_correction_disable) > + ctl |= > PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; > } > > return ctl; > -- > 2.25.1
