Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Medium] The patch silently fixes a register programming bug, changing the programmed HPD interrupt debounce thresholds, despite the commit message claiming 'the only purpose of increasing human readability'. - [Low] Unused legacy macros were left in the header file after their usage was removed. --
--- Patch [11]: [PATCH v3 11/11] drm/mediatek: mtk_dp: Clarify XTAL freq and Debounce registers --- commit a0d0ec4a08e7bb60a4d55891bd6e55ba3b2ab740 Author: AngeloGioacchino Del Regno <[email protected]> drm/mediatek: mtk_dp: Clarify XTAL freq and Debounce registers This patch refactors the initialization of the crystal frequency and transmitter interrupt debounce registers in the MediaTek DP driver to use FIELD_PREP_CONST for better readability. > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c > b/drivers/gpu/drm/mediatek/mtk_dp.c > index 868d918a0b161..4403a25784d4e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp.c > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c [ ... ] > @@ -1260,28 +1266,29 @@ static void > mtk_dp_initialize_aux_hpd_detect_settings(struct mtk_dp *mtk_dp) > > static void mtk_dp_initialize_hpd_detect_settings(struct mtk_dp *mtk_dp) > { > - u32 val; > - > /* Mask AUX TOP interrupt, as this uses transmitter for HPD */ > mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_IRQ_MASK, > AUX_TOP_IRQ_MSK, AUX_TOP_IRQ_MSK); > > - /* Debounce threshold */ > + /* Set Hotplug debounce threshold time: xtal_period * deb_thd */ > mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410, > 8, HPD_DEB_THD_DP_TRANS_P0_MASK); > > - val = (HPD_INT_THD_DP_TRANS_P0_LOWER_500US | > - HPD_INT_THD_DP_TRANS_P0_UPPER_1100US) << 4; > - mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410, > - val, HPD_INT_THD_DP_TRANS_P0_MASK); > - > /* > - * Connect threshold 1.5ms + 5 x 0.1ms = 2ms > - * Disconnect threshold 1.5ms + 5 x 0.1ms = 2ms > + * Set interrupt debounce threshold time > + * VAL | 0 1 2 3 INT_THD > + * Low | 100 300 500 700 uS > + * High | 700 900 1100 1300 uS > */ > - val = (5 << 8) | (5 << 12); > mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410, > - val, > + FIELD_PREP_CONST(HPD_INT_LOW_THD_DP_TRANS_P0_MASK, > 2) | > + FIELD_PREP_CONST(HPD_INT_HIGH_THD_DP_TRANS_P0_MASK, > 2), > + HPD_INT_THD_DP_TRANS_P0_MASK); [Severity: Medium] The commit message states the patch has "the only purpose of increasing human readability", but does this actually fix a bug in the old code? The original code calculated the values with an extra shift: val = (HPD_INT_THD_DP_TRANS_P0_LOWER_500US | HPD_INT_THD_DP_TRANS_P0_UPPER_1100US) << 4; Since those macros were already shifted by 4 and 6, the extra shift by 4 resulted in val = 0xA00. When updated with the 0xF0 mask, this effectively wrote 0 to the register. The new code correctly programs 0xA0. Could the commit message be updated to mention this functional change? > + > + /* Connection and Disconnection thresholds: 1.5ms + (5 x 0.1) ms = 2ms > */ > + mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410, [ ... ] > diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h > b/drivers/gpu/drm/mediatek/mtk_dp_reg.h > index 9caf743f4fe61..ce47b99dddc43 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h > +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h > @@ -253,6 +253,8 @@ > #define MTK_DP_TRANS_P0_3410 0x1410 > #define HPD_DEB_THD_DP_TRANS_P0_MASK GENMASK(3, 0) > #define HPD_INT_THD_DP_TRANS_P0_MASK GENMASK(7, 4) > +#define HPD_INT_HIGH_THD_DP_TRANS_P0_MASK GENMASK(7, 6) > +#define HPD_INT_LOW_THD_DP_TRANS_P0_MASK GENMASK(5, 4) > #define HPD_INT_THD_DP_TRANS_P0_LOWER_500US (2 << 4) > #define HPD_INT_THD_DP_TRANS_P0_UPPER_1100US (2 << 6) [Severity: Low] This isn't a bug, but are these legacy macros still needed? The code no longer uses HPD_INT_THD_DP_TRANS_P0_LOWER_500US or HPD_INT_THD_DP_TRANS_P0_UPPER_1100US after this patch. -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=11
