On Mon, Jun 29, 2026 at 10:14:25PM +0800, Yongxing Mou wrote: > From: Abhinav Kumar <[email protected]> > > In the DP MST architecture, stream 1 shares the same link clock as > stream 0 but uses different register offsets within the same link > register space. Use the dp_panel's stream_id to select the correct > register offsets for stream 1 in dp_catalog. Also add stream 1 > register defines. > > Streams 2 and 3 are not covered here, as they use separate link clocks > and require separate handling.
I think, this is no longer true. I see them being handled here. > > Signed-off-by: Abhinav Kumar <[email protected]> > Signed-off-by: Yongxing Mou <[email protected]> > --- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 78 ++++++++++++++++++++++++------ > drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 +- > drivers/gpu/drm/msm/dp/dp_display.c | 24 +++++++++- > drivers/gpu/drm/msm/dp/dp_panel.c | 94 > ++++++++++++++++++++++++++++++++++++- > drivers/gpu/drm/msm/dp/dp_panel.h | 4 ++ > drivers/gpu/drm/msm/dp/dp_reg.h | 44 +++++++++++++++++ > 6 files changed, 229 insertions(+), 19 deletions(-) > > @@ -397,7 +442,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct > msm_dp_ctrl_private *ctrl, > /* > * RMW: Called from atomic_enable(). Serialized by the DRM atomic > framework. > */ > - config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); > + if (msm_dp_panel->stream_id == DP_STREAM_0) > + config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); Why is it being done only for stream 0? > > if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) > config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ > @@ -412,7 +458,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct > msm_dp_ctrl_private *ctrl, > > drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", > config); > > - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); > + msm_dp_write_stream_link(ctrl, msm_dp_panel->stream_id, > REG_DP_CONFIGURATION_CTRL, config); > } > > static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl, > @@ -2514,7 +2560,7 @@ static void msm_dp_ctrl_config_msa(struct > msm_dp_ctrl_private *ctrl, > nvid = temp; > } > > - if (is_ycbcr_420) > + if (panel->msm_dp_mode.out_fmt_is_yuv_420) Unrelated change. > mvid /= 2; > > if (link_rate_hbr2 == rate) > @@ -2524,8 +2570,8 @@ static void msm_dp_ctrl_config_msa(struct > msm_dp_ctrl_private *ctrl, > nvid *= 3; > > drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); > - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); > - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); > + msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_MVID, > mvid); > + msm_dp_write_stream_link(ctrl, panel->stream_id, REG_DP_SOFTWARE_NVID, > nvid); > } > > int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, > @@ -2597,14 +2643,14 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl > *msm_dp_ctrl, struct msm_dp_panel * > > msm_dp_ctrl_lane_mapping(ctrl); > msm_dp_setup_peripheral_flush(ctrl); > - msm_dp_ctrl_config_ctrl_link(ctrl, panel); > + if (panel->stream_id == DP_STREAM_0) > + msm_dp_ctrl_config_ctrl_link(ctrl, panel); Why is it only done for stream 0? Split all unrelated changes. > > msm_dp_ctrl_configure_source_params(ctrl, panel); > > msm_dp_ctrl_config_msa(ctrl, > - ctrl->link->link_params.rate, > - pixel_rate_orig, > - panel->msm_dp_mode.out_fmt_is_yuv_420); > + panel, ctrl->link->link_params.rate, > + pixel_rate_orig); > > msm_dp_panel_clear_dsc_dto(panel); > > diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h > index 3689642b7fc0..310e5a1cc934 100644 > --- a/drivers/gpu/drm/msm/dp/dp_reg.h > +++ b/drivers/gpu/drm/msm/dp/dp_reg.h > @@ -332,6 +332,50 @@ > #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) > #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) > > +#define REG_DP1_CONFIGURATION_CTRL (0x00000400) > +#define REG_DP1_SOFTWARE_MVID (0x00000414) > +#define REG_DP1_SOFTWARE_NVID (0x00000418) > +#define REG_DP1_TOTAL_HOR_VER (0x0000041C) lowercase hex. Also are there no registers from the same register space? > +#define REG_DP1_START_HOR_VER_FROM_SYNC (0x00000420) > +#define REG_DP1_HSYNC_VSYNC_WIDTH_POLARITY (0x00000424) > +#define REG_DP1_ACTIVE_HOR_VER (0x00000428) > +#define REG_DP1_MISC1_MISC0 (0x0000042C) > +#define MMSS_DP1_GENERIC0_0 (0x00000490) > +#define MMSS_DP1_GENERIC0_1 (0x00000494) > +#define MMSS_DP1_GENERIC0_2 (0x00000498) > +#define MMSS_DP1_GENERIC0_3 (0x0000049C) > +#define MMSS_DP1_GENERIC0_4 (0x000004A0) > +#define MMSS_DP1_GENERIC0_5 (0x000004A4) > +#define MMSS_DP1_GENERIC0_6 (0x000004A8) > +#define MMSS_DP1_GENERIC0_7 (0x000004AC) > +#define MMSS_DP1_GENERIC0_8 (0x000004B0) > +#define MMSS_DP1_GENERIC0_9 (0x000004B4) > +#define MMSS_DP1_SDP_CFG (0x000004E0) > +#define MMSS_DP1_SDP_CFG2 (0x000004E4) > +#define MMSS_DP1_SDP_CFG3 (0x000004E8) > + > +#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) > +#define REG_MSTLINK_SOFTWARE_MVID (0x00000040) > +#define REG_MSTLINK_SOFTWARE_NVID (0x00000044) Why are they not REG_DP_MSTLINK? > +#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) > +#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004C) > +#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050) > +#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054) > +#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058) > +#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000BC) > +#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000C0) > +#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000C4) > +#define MMSS_DP_MSTLINK_GENERIC0_3 (0x000000C8) > +#define MMSS_DP_MSTLINK_GENERIC0_4 (0x000000CC) > +#define MMSS_DP_MSTLINK_GENERIC0_5 (0x000000D0) > +#define MMSS_DP_MSTLINK_GENERIC0_6 (0x000000D4) > +#define MMSS_DP_MSTLINK_GENERIC0_7 (0x000000D8) > +#define MMSS_DP_MSTLINK_GENERIC0_8 (0x000000DC) > +#define MMSS_DP_MSTLINK_GENERIC0_9 (0x000000E0) > +#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c) > +#define MMSS_DP_MSTLINK_SDP_CFG2 (0x0000011c) > +#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114) > + > #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) > > #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) > > -- > 2.43.0 > -- With best wishes Dmitry
