Add basic support for the Image Resizer hardware found in some MediaTek Display Controller IPs, like the one found in MT8196.
This is currently set in bypass mode and used to pass the frame buffer from a RSZ input component to supported RSZ outputs. Full implementation of hardware-accelerated DRM scaling will be done later. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index e1873a20e64b..453a4a9ad565 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -56,6 +56,10 @@ #define POSTMASK_RELAY_MODE BIT(0) #define DISP_REG_POSTMASK_SIZE 0x0030 +#define DISP_REG_RSZ_EN 0x0000 +#define DISP_REG_RSZ_INPUT_SIZE 0x0010 +#define DISP_REG_RSZ_OUTPUT_SIZE 0x0014 + #define DISP_REG_UFO_START 0x0000 #define UFO_BYPASS BIT(2) @@ -230,6 +234,16 @@ static void mtk_postmask_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN); } +static void mtk_rsz_config(struct mtk_ddp_comp *comp, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_REG_RSZ_INPUT_SIZE); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_REG_RSZ_OUTPUT_SIZE); +} + static void mtk_ufoe_start(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); @@ -414,6 +428,12 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = { .get_num_formats = mtk_rdma_get_num_formats, }; +static const struct mtk_ddp_comp_funcs ddp_rsz = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_rsz_config, +}; + static const struct mtk_ddp_comp_funcs ddp_tdshp = { .clk_enable = mtk_tdshp_clk_enable, .clk_disable = mtk_tdshp_clk_disable, @@ -489,6 +509,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_POSTMASK] = "postmask", [MTK_DISP_PWM] = "pwm", [MTK_DISP_RDMA] = "rdma", + [MTK_DISP_RSZ] = "resizer", [MTK_DISP_TDSHP] = "tdshp", [MTK_DISP_UFOE] = "ufoe", [MTK_DISP_WDMA] = "wdma", @@ -517,6 +538,7 @@ static const struct mtk_ddp_comp_funcs *mtk_ddp_funcs[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_POSTMASK] = &ddp_postmask, [MTK_DISP_PWM] = NULL, [MTK_DISP_RDMA] = &ddp_rdma, + [MTK_DISP_RSZ] = &ddp_rsz, [MTK_DISP_TDSHP] = &ddp_tdshp, [MTK_DISP_UFOE] = &ddp_ufoe, [MTK_DISP_WDMA] = &ddp_wdma, @@ -677,6 +699,7 @@ bool mtk_ddp_comp_is_internal_comp(enum mtk_ddp_comp_type type) case MTK_DISP_DITHER: case MTK_DISP_OD: case MTK_DISP_POSTMASK: + case MTK_DISP_RSZ: case MTK_DISP_UFOE: return true; default: diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6cf285f1879d..82d844b6abf7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -714,6 +714,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8195-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8196-disp-rsz", + .data = (void *)MTK_DISP_RSZ }, { .compatible = "mediatek,mt8196-disp-tdshp", .data = (void *)MTK_DISP_TDSHP }, { .compatible = "mediatek,mt8173-disp-ufoe", -- 2.54.0
