Hi all, Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/amd/display/dc/core/dc.c
between commit:
d73f4e118dc4c ("drm/amd/display: check GRPH_FLIP status before sending event")
from the drm-fixes tree and commits:
f64a9be565368 ("drm/amd/display: check GRPH_FLIP status before sending event")
72b94048020ce ("drm/amd/display: limit reuse dsc capable bootup timing")
98e08a815ef60 ("drm/amd/display: Tear down dangling pipe on boot to fix s0i3")
2a5810782369b ("drm/amd/display: program dither on all OPP heads under ODM
combine")
f3403ab74a29f ("drm/amd/display: Add block sequence support for bandwidth
programming operations")
991e0516a8072 ("drm/amd/display: use kvzalloc to allocate struct dc")
9e0896fa6f7db ("drm/amd/display: avoid large stack allocation in
commit_planes_do_stream_update_sequence")
c1199393ec559 ("drm/amd/display: Refactor surface_update_flags to flat struct
with helpers")
b008c67efb36b ("drm/amd/display: Introduce dc_plane_cm and migrate surface
update color path")
from the drm tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
diff --combined drivers/gpu/drm/amd/display/dc/core/dc.c
index e25b94b65daca,8d77158229f1b..0000000000000
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@@ -769,22 -769,23 +769,23 @@@ void dc_stream_set_dither_option(struc
{
struct bit_depth_reduction_params params;
struct dc_link *link = stream->link;
- struct pipe_ctx *pipes = NULL;
+ struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
+ struct pipe_ctx *otg_master;
+ struct pipe_ctx *opp_heads[MAX_PIPES];
+ int opp_cnt;
int i;
- for (i = 0; i < MAX_PIPES; i++) {
- if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
- stream) {
- pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
- break;
- }
- }
-
- if (!pipes)
+ otg_master = resource_get_otg_master_for_stream(res_ctx, stream);
+ if (!otg_master)
return;
if (option > DITHER_OPTION_MAX)
return;
+ opp_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx,
opp_heads);
+
+ if (opp_cnt == 0)
+ return;
+
dc_exit_ips_for_hw_access(stream->ctx->dc);
stream->dither_option = option;
@@@ -793,16 -794,30 +794,30 @@@
resource_build_bit_depth_reduction_params(stream, ¶ms);
stream->bit_depth_params = params;
- if (pipes->plane_res.xfm &&
- pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
- pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
- pipes->plane_res.xfm,
- pipes->plane_res.scl_data.lb_params.depth,
- &stream->bit_depth_params);
- }
+ /*
+ * Program bit-depth reduction (dither) on every OPP head of the
+ * stream. Under ODM combine there is more than one OPP head and they
+ * must all be kept in sync, otherwise (e.g. when CRC capture requests
+ * dither off) a secondary ODM segment can keep dither enabled and
+ * produce a different CRC than the primary segment.
+ */
+ for (i = 0; i < opp_cnt; i++) {
+ struct pipe_ctx *opp_head = opp_heads[i];
- pipes->stream_res.opp->funcs->
- opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms);
+ if (opp_head->plane_res.xfm &&
+
opp_head->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
+
opp_head->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
+ opp_head->plane_res.xfm,
+ opp_head->plane_res.scl_data.lb_params.depth,
+ &stream->bit_depth_params);
+ }
+
+ if (opp_head->stream_res.opp &&
+
opp_head->stream_res.opp->funcs->opp_program_bit_depth_reduction) {
+
opp_head->stream_res.opp->funcs->opp_program_bit_depth_reduction(
+ opp_head->stream_res.opp, ¶ms);
+ }
+ }
}
bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state
*stream)
@@@ -1930,6 -1945,13 +1945,13 @@@ bool dc_validate_boot_timing(const stru
struct display_stream_compressor *dsc = NULL;
struct dcn_dsc_state dsc_state = {0};
+ if (dc->ctx->dce_version < DCN_VERSION_4_2) {
+ /*vbios enabled eDP dsc for one of DCN315 only but it
has known issue,
+ since there is no production bios update, block it
there*/
+ DC_LOG_DEBUG("boot timing validation failed due to
unsupported DSC on this ASIC\n");
+ return false;
+ }
+
/* Find DSC associated with this timing generator */
if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) {
dsc = dc->res_pool->dscs[tg_inst];
@@@ -2310,7 -2332,7 +2332,7 @@@ static enum dc_status dc_commit_state_n
for (i = 0; i < context->stream_count; i++) {
uint32_t prev_dsc_changed =
context->streams[i]->update_flags.bits.dsc_changed;
- context->streams[i]->update_flags.raw = 0xFFFFFFFF;
+
stream_update_flags_set_full(&context->streams[i]->update_flags);
context->streams[i]->update_flags.bits.dsc_changed =
prev_dsc_changed;
}
@@@ -2416,7 -2438,7 +2438,7 @@@
/* Clear update flags that were set earlier to avoid redundant
programming */
for (i = 0; i < context->stream_count; i++) {
- context->streams[i]->update_flags.raw = 0x0;
+ stream_update_flags_clear(&context->streams[i]->update_flags);
}
old_state = dc->current_state;
@@@ -2764,7 -2786,7 +2786,7 @@@ static bool is_surface_in_context
static struct surface_update_descriptor get_plane_info_update_type(const
struct dc_surface_update *u)
{
- union surface_update_flags *update_flags = &u->surface->update_flags;
+ struct pipe_update_bits *update_bits = &u->surface->update_bits;
struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_NONE };
if (!u->plane_info)
@@@ -2774,37 -2796,37 +2796,37 @@@
elevate_update_type(&update_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
if (u->plane_info->color_space != u->surface->color_space) {
- update_flags->bits.color_space_change = 1;
+ update_bits->color_space_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
}
if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
- update_flags->bits.horizontal_mirror_change = 1;
+ update_bits->horizontal_mirror_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
}
if (u->plane_info->rotation != u->surface->rotation) {
- update_flags->bits.rotation_change = 1;
+ update_bits->rotation_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
if (u->plane_info->format != u->surface->format) {
- update_flags->bits.pixel_format_change = 1;
+ update_bits->pixel_format_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
if (u->plane_info->stereo_format != u->surface->stereo_format) {
- update_flags->bits.stereo_format_change = 1;
+ update_bits->stereo_format_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
- update_flags->bits.per_pixel_alpha_change = 1;
+ update_bits->per_pixel_alpha_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
}
if (u->plane_info->global_alpha_value !=
u->surface->global_alpha_value) {
- update_flags->bits.global_alpha_change = 1;
+ update_bits->global_alpha_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
}
@@@ -2816,7 -2838,7 +2838,7 @@@
* stutter period calculation. Triggering a full update will
* recalculate stutter period.
*/
- update_flags->bits.dcc_change = 1;
+ update_bits->dcc_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
@@@ -2825,25 -2847,25 +2847,25 @@@
/* different bytes per element will require full bandwidth
* and DML calculation
*/
- update_flags->bits.bpp_change = 1;
+ update_bits->bpp_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
if (u->plane_info->plane_size.surface_pitch !=
u->surface->plane_size.surface_pitch
|| u->plane_info->plane_size.chroma_pitch !=
u->surface->plane_size.chroma_pitch) {
- update_flags->bits.plane_size_change = 1;
+ update_bits->plane_size_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
}
const struct dc_tiling_info *tiling = &u->plane_info->tiling_info;
if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) {
- update_flags->bits.swizzle_change = 1;
+ update_bits->swizzle_change = 1;
if (tiling->flags.avoid_full_update_on_tiling_change) {
elevate_update_type(&update_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
} else {
- update_flags->bits.bandwidth_change = 1;
+ update_bits->bandwidth_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
}
@@@ -2853,10 -2875,10 +2875,10 @@@
}
static struct surface_update_descriptor get_scaling_info_update_type(
- const struct dc_check_config *check_config,
- const struct dc_surface_update *u)
+ const struct dc_check_config *check_config,
+ const struct dc_surface_update *u)
{
- union surface_update_flags *update_flags = &u->surface->update_flags;
+ struct pipe_update_bits *update_bits = &u->surface->update_bits;
struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_NONE };
if (!u->scaling_info)
@@@ -2873,26 -2895,26 +2895,26 @@@
|| u->scaling_info->clip_rect.height !=
u->surface->clip_rect.height
|| u->scaling_info->scaling_quality.integer_scaling !=
u->surface->scaling_quality.integer_scaling) {
- update_flags->bits.scaling_change = 1;
+ update_bits->scaling_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
if (u->scaling_info->src_rect.width > u->surface->src_rect.width
|| u->scaling_info->src_rect.height >
u->surface->src_rect.height)
/* Making src rect bigger requires a bandwidth change */
- update_flags->bits.clock_change = 1;
+ update_bits->clock_change = 1;
if ((u->scaling_info->dst_rect.width <
u->surface->dst_rect.width
|| u->scaling_info->dst_rect.height <
u->surface->dst_rect.height)
&& (u->scaling_info->dst_rect.width <
u->surface->src_rect.width
|| u->scaling_info->dst_rect.height <
u->surface->src_rect.height))
/* Making dst rect smaller requires a bandwidth change
*/
- update_flags->bits.bandwidth_change = 1;
+ update_bits->bandwidth_change = 1;
if (u->scaling_info->src_rect.width >
(int)check_config->max_optimizable_video_width &&
(u->scaling_info->clip_rect.width >
u->surface->clip_rect.width ||
u->scaling_info->clip_rect.height >
u->surface->clip_rect.height))
/* Changing clip size of a large surface may result in
MPC slice count change */
- update_flags->bits.bandwidth_change = 1;
+ update_bits->bandwidth_change = 1;
}
if (u->scaling_info->src_rect.x != u->surface->src_rect.x
@@@ -2902,7 -2924,7 +2924,7 @@@
|| u->scaling_info->dst_rect.x != u->surface->dst_rect.x
|| u->scaling_info->dst_rect.y !=
u->surface->dst_rect.y) {
elevate_update_type(&update_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
- update_flags->bits.position_change = 1;
+ update_bits->position_change = 1;
}
return update_type;
@@@ -2913,15 -2935,15 +2935,15 @@@ static struct surface_update_descripto
struct dc_surface_update *u)
{
struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_NONE };
- union surface_update_flags *update_flags = &u->surface->update_flags;
+ struct pipe_update_bits *update_bits = &u->surface->update_bits;
if (u->surface->force_full_update) {
- update_flags->raw = 0xFFFFFFFF;
+ dc_pipe_update_bits_set_full(update_bits);
elevate_update_type(&overall_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
return overall_type;
}
- update_flags->raw = 0; // Reset all flags
+ dc_pipe_update_bits_clear(update_bits);
struct surface_update_descriptor inner_type =
get_plane_info_update_type(u);
@@@ -2931,87 -2953,112 +2953,112 @@@
elevate_update_type(&overall_type, inner_type.update_type,
inner_type.lock_descriptor);
if (u->flip_addr) {
- update_flags->bits.addr_update = 1;
+ update_bits->addr_update = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
if (u->flip_addr->address.tmz_surface !=
u->surface->address.tmz_surface) {
- update_flags->bits.tmz_changed = 1;
+ update_bits->tmz_changed = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
}
if (u->in_transfer_func) {
- update_flags->bits.in_transfer_func_change = 1;
+ update_bits->in_transfer_func_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
}
if (u->input_csc_color_matrix) {
- update_flags->bits.input_csc_change = 1;
+ update_bits->input_csc_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
}
if (u->cursor_csc_color_matrix) {
- update_flags->bits.cursor_csc_color_matrix_change = 1;
+ update_bits->cursor_csc_color_matrix_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
}
if (u->coeff_reduction_factor) {
- update_flags->bits.coeff_reduction_change = 1;
+ update_bits->coeff_reduction_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
}
if (u->gamut_remap_matrix) {
- update_flags->bits.gamut_remap_change = 1;
+ update_bits->gamut_remap_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
}
- if (u->blend_tf || (u->gamma && dce_use_lut(u->plane_info ?
u->plane_info->format : u->surface->format))) {
- update_flags->bits.gamma_change = 1;
+ if ((u->cm && u->cm->flags.bits.blend_enable) ||
+ (u->gamma && dce_use_lut(u->plane_info ?
u->plane_info->format : u->surface->format))) {
+ update_bits->gamma_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
}
- if (u->lut3d_func || u->func_shaper) {
- update_flags->bits.lut_3d = 1;
+ if (u->cm && (u->cm->flags.bits.lut3d_enable ||
u->cm->flags.bits.shaper_enable)) {
+ update_bits->lut_3d = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
}
+ if (u->cm && u->cm->flags.bits.lut3d_dma_enable !=
u->surface->cm.flags.bits.lut3d_dma_enable &&
+ u->cm->flags.bits.lut3d_enable &&
u->surface->cm.flags.bits.lut3d_enable) {
+ /* Toggling 3DLUT loading between DMA and Host is illegal */
+ BREAK_TO_DEBUGGER();
+ }
+
+ if (u->cm && u->cm->flags.bits.lut3d_enable &&
!u->cm->flags.bits.lut3d_dma_enable) {
+ /* Host loading 3DLUT requires full update but only stream lock
*/
+ elevate_update_type(&overall_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_STREAM);
+ }
+
if (u->hdr_mult.value)
if (u->hdr_mult.value != u->surface->hdr_mult.value) {
// TODO: Should be fast?
- update_flags->bits.hdr_mult = 1;
+ update_bits->hdr_mult = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_MED,
LOCK_DESCRIPTOR_STREAM);
}
if (u->sdr_white_level_nits)
if (u->sdr_white_level_nits !=
u->surface->sdr_white_level_nits) {
// TODO: Should be fast?
- update_flags->bits.sdr_white_level_nits = 1;
+ update_bits->sdr_white_level_nits = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
if (u->cm_hist_control) {
- update_flags->bits.cm_hist_change = 1;
+ update_bits->cm_hist_change = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST,
LOCK_DESCRIPTOR_STREAM);
}
- if (u->cm2_params) {
- if (u->cm2_params->component_settings.shaper_3dlut_setting !=
u->surface->mcm_shaper_3dlut_setting
- ||
u->cm2_params->component_settings.lut1d_enable != u->surface->mcm_lut1d_enable
- || u->cm2_params->cm2_luts.lut3d_data.lut3d_src
!= u->surface->mcm_luts.lut3d_data.lut3d_src) {
- update_flags->bits.mcm_transfer_function_enable_change
= 1;
+
+ if (u->cm) {
+ const union dc_plane_cm_flags blend_only_flags = {
+ .bits = {
+ .blend_enable = 1,
+ }
+ };
+
+ if (u->cm->flags.bits.shaper_enable !=
u->surface->cm.flags.bits.shaper_enable
+ || u->cm->flags.bits.blend_enable !=
u->surface->cm.flags.bits.blend_enable
+ || u->cm->flags.bits.lut3d_enable !=
u->surface->cm.flags.bits.lut3d_enable
+ || u->cm->flags.bits.lut3d_dma_enable !=
u->surface->cm.flags.bits.lut3d_dma_enable) {
+ update_bits->mcm_transfer_function_enable_change = 1;
+ elevate_update_type(&overall_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
+ }
+
+ if ((u->cm->flags.all != blend_only_flags.all &&
u->cm->flags.all != 0) ||
+ (u->surface->cm.flags.all !=
blend_only_flags.all && u->surface->cm.flags.all != 0)) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
}
- if (update_flags->bits.lut_3d &&
- u->surface->mcm_luts.lut3d_data.lut3d_src !=
DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {
+ if (update_bits->lut_3d &&
+ !u->surface->cm.flags.bits.lut3d_dma_enable) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
if (check_config->enable_legacy_fast_update &&
- (update_flags->bits.gamma_change ||
- update_flags->bits.gamut_remap_change ||
- update_flags->bits.input_csc_change ||
- update_flags->bits.cm_hist_change ||
- update_flags->bits.coeff_reduction_change)) {
+ (update_bits->gamma_change ||
+ update_bits->gamut_remap_change ||
+ update_bits->input_csc_change ||
+ update_bits->cm_hist_change ||
+ update_bits->coeff_reduction_change)) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL,
LOCK_DESCRIPTOR_GLOBAL);
}
return overall_type;
@@@ -3036,7 -3083,7 +3083,7 @@@ static void force_immediate_gsl_plane_f
if (has_flip_immediate_plane && surface_count > 1) {
for (i = 0; i < surface_count; i++) {
if (updates[i].surface->flip_immediate)
-
updates[i].surface->update_flags.bits.addr_update = 1;
+ updates[i].surface->update_bits.addr_update = 1;
}
}
}
@@@ -3191,9 -3238,9 +3238,9 @@@ struct surface_update_descriptor dc_che
struct dc_stream_update *stream_update)
{
if (stream_update)
- stream_update->stream->update_flags.raw = 0;
+ stream_update_flags_clear(&stream_update->stream->update_flags);
for (int i = 0; i < surface_count; i++)
- updates[i].surface->update_flags.raw = 0;
+ dc_pipe_update_bits_clear(&updates[i].surface->update_bits);
return check_update_surfaces_for_stream(check_config, updates,
surface_count, stream_update);
}
@@@ -3304,24 -3351,55 +3351,55 @@@ static void copy_surface_update_to_plan
sizeof(struct dc_transfer_func_distributed_points));
}
- if (srf_update->cm2_params) {
- surface->mcm_shaper_3dlut_setting =
srf_update->cm2_params->component_settings.shaper_3dlut_setting;
- surface->mcm_lut1d_enable =
srf_update->cm2_params->component_settings.lut1d_enable;
- surface->mcm_luts = srf_update->cm2_params->cm2_luts;
+ /* Shaper, 3DLUT, 1DLUT */
+ if (srf_update->cm) {
+ struct kref refcount = surface->cm.refcount;
+
+ memcpy(&surface->cm, srf_update->cm, sizeof(surface->cm));
+ surface->cm.refcount = refcount;
+
+ #ifndef TRIM_CM2
+ /* Populate mcm_luts from cm for legacy consumers (dml2, hwseq)
*/
+ surface->mcm_luts.lut1d_func = &surface->cm.blend_func;
+ surface->mcm_luts.shaper = &surface->cm.shaper_func;
+ if (srf_update->cm->flags.bits.lut3d_dma_enable) {
+ surface->mcm_luts.lut3d_data.lut3d_src =
DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM;
+ surface->mcm_luts.lut3d_data.gpu_mem_params.addr =
surface->cm.lut3d_dma.addr;
+ surface->mcm_luts.lut3d_data.gpu_mem_params.layout =
+ (surface->cm.lut3d_dma.swizzle ==
CM_LUT_3D_SWIZZLE_LINEAR_RGB) ?
+
DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB :
+ (surface->cm.lut3d_dma.swizzle ==
CM_LUT_3D_SWIZZLE_LINEAR_BGR) ?
+
DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR :
+ DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR;
+
surface->mcm_luts.lut3d_data.gpu_mem_params.format_params.format =
+ (surface->cm.lut3d_dma.format ==
CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB) ?
+
DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB :
+ (surface->cm.lut3d_dma.format ==
CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB) ?
+
DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB :
+
DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10;
+
surface->mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias =
+ surface->cm.lut3d_dma.bias;
+
surface->mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale =
+ surface->cm.lut3d_dma.scale;
+
surface->mcm_luts.lut3d_data.gpu_mem_params.component_order =
+ DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA;
+ surface->mcm_luts.lut3d_data.gpu_mem_params.size =
DC_CM2_GPU_MEM_SIZE_TRANSFORMED;
+ surface->mcm_luts.lut3d_data.mpc_3dlut_enable =
(srf_update->cm->flags.bits.lut3d_enable != 0);
+ } else {
+ surface->mcm_luts.lut3d_data.lut3d_src =
DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM;
+ surface->mcm_luts.lut3d_data.lut3d_func =
&surface->cm.lut3d_func;
+ }
+
+ if (srf_update->cm->flags.bits.shaper_enable &&
+ srf_update->cm->flags.bits.lut3d_enable)
+ surface->mcm_shaper_3dlut_setting =
DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT;
+ else if (srf_update->cm->flags.bits.shaper_enable)
+ surface->mcm_shaper_3dlut_setting =
DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER;
+ else
+ surface->mcm_shaper_3dlut_setting =
DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL;
+ #endif /* TRIM_CM2 */
}
- if (srf_update->func_shaper) {
- memcpy(&surface->in_shaper_func, srf_update->func_shaper,
- sizeof(surface->in_shaper_func));
-
- if (surface->mcm_shaper_3dlut_setting >=
DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER)
- surface->mcm_luts.shaper = &surface->in_shaper_func;
- }
-
- if (srf_update->lut3d_func)
- memcpy(&surface->lut3d_func, srf_update->lut3d_func,
- sizeof(surface->lut3d_func));
-
if (srf_update->hdr_mult.value)
surface->hdr_mult =
srf_update->hdr_mult;
@@@ -3330,15 -3408,10 +3408,10 @@@
surface->sdr_white_level_nits =
srf_update->sdr_white_level_nits;
- if (srf_update->blend_tf) {
- memcpy(&surface->blend_tf, srf_update->blend_tf,
- sizeof(surface->blend_tf));
-
- if (surface->mcm_lut1d_enable)
- surface->mcm_luts.lut1d_func = &surface->blend_tf;
- }
-
- if (srf_update->cm2_params || srf_update->blend_tf)
+ if (srf_update->cm &&
+ (srf_update->cm->flags.bits.blend_enable ||
+ srf_update->cm->flags.bits.shaper_enable ||
+ srf_update->cm->flags.bits.lut3d_enable))
surface->lut_bank_a = !surface->lut_bank_a;
if (srf_update->input_csc_color_matrix)
@@@ -3714,11 -3787,11 +3787,11 @@@ static bool update_planes_and_stream_st
if (update_type == UPDATE_TYPE_FULL) {
if (stream_update) {
uint32_t dsc_changed =
stream_update->stream->update_flags.bits.dsc_changed;
- stream_update->stream->update_flags.raw = 0xFFFFFFFF;
+
stream_update_flags_set_full(&stream_update->stream->update_flags);
stream_update->stream->update_flags.bits.dsc_changed =
dsc_changed;
}
for (i = 0; i < surface_count; i++)
- srf_updates[i].surface->update_flags.raw = 0xFFFFFFFF;
+
dc_pipe_update_bits_set_full(&srf_updates[i].surface->update_bits);
}
if (update_type >= update_surface_trace_level)
@@@ -3767,7 -3840,7 +3840,7 @@@
if (update_type != UPDATE_TYPE_MED)
continue;
- if (surface->update_flags.bits.position_change) {
+ if (surface->update_bits.position_change) {
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx =
&context->res_ctx.pipe_ctx[j];
@@@ -4205,8 -4278,8 +4278,8 @@@ static void commit_planes_do_stream_upd
hwss_add_dc_set_optimized_required(&seq_state, dc, true);
} else {
- if
(get_seamless_boot_stream_count(context) == 0)
-
hwss_add_prepare_bandwidth(&seq_state, dc, dc->current_state);
+ if
(get_seamless_boot_stream_count(context) == 0 &&
dc->hwss.prepare_bandwidth_sequence)
+
dc->hwss.prepare_bandwidth_sequence(dc, dc->current_state, &seq_state);
hwss_add_link_set_dpms_on(&seq_state,
dc->current_state, dpms_pipe_ctx);
}
} else if
(pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change &&
stream_update->output_color_space
@@@ -4550,14 -4623,23 +4623,23 @@@ static void build_dmub_update_dirty_rec
}
}
- static bool check_address_only_update(union surface_update_flags update_flags)
+ /**
+ * dc_check_address_only_update - Check if addr_update is the sole flag set
+ *
+ * @update_bits: The pipe update bits to check
+ *
+ * Determines whether an update contains only an address change with no other
+ * pending updates.
+ *
+ * Return: %true if addr_update is the sole bit set, %false otherwise.
+ */
+ bool dc_check_address_only_update(struct pipe_update_bits update_bits)
{
- union surface_update_flags addr_only_update_flags;
- addr_only_update_flags.raw = 0;
- addr_only_update_flags.bits.addr_update = 1;
+ struct pipe_update_bits check = update_bits; /* 1. Copy all flags from
input */
- return update_flags.bits.addr_update &&
- !(update_flags.raw & ~addr_only_update_flags.raw);
+ check.addr_update = 0; /* 2. Zero the
addr_update bit in the copy */
+ return update_bits.addr_update && /* 3. Check addr_update
was set in original */
+ !dc_pipe_update_bits_is_any_set(&check); /* 4. Check no
other bits remain in the copy */
}
/**
@@@ -4617,7 -4699,7 +4699,7 @@@ static void commit_plane_for_stream_off
continue;
/* update pipe context for plane */
- if
(pipe_ctx->plane_state->update_flags.bits.addr_update)
+ if (pipe_ctx->plane_state->update_bits.addr_update)
dc->hwss.update_plane_addr(dc, pipe_ctx);
}
}
@@@ -4655,8 -4737,8 +4737,8 @@@ static void commit_planes_for_stream_fa
should_offload_fams2_flip = true;
for (i = 0; i < surface_count; i++) {
if (srf_updates[i].surface &&
-
srf_updates[i].surface->update_flags.raw &&
-
!check_address_only_update(srf_updates[i].surface->update_flags)) {
+
dc_pipe_update_bits_is_any_set(&srf_updates[i].surface->update_bits) &&
+
!dc_check_address_only_update(srf_updates[i].surface->update_bits)) {
/* more than address update, need to acquire
FAMS2 lock */
should_offload_fams2_flip = false;
break;
@@@ -4747,7 -4829,7 +4829,7 @@@
* so no need to clear here.
*/
if (top_pipe_to_program->stream)
- top_pipe_to_program->stream->update_flags.raw = 0;
+
stream_update_flags_clear(&top_pipe_to_program->stream->update_flags);
}
static void commit_planes_for_stream(struct dc *dc,
@@@ -5073,11 -5155,9 +5155,9 @@@
if (!should_update_pipe_for_plane(context,
pipe_ctx, plane_state))
continue;
- if (srf_updates[i].cm2_params &&
-
srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src ==
-
DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM &&
-
srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting ==
-
DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT &&
+ if (srf_updates[i].cm &&
+
srf_updates[i].cm->flags.bits.lut3d_enable &&
+
srf_updates[i].cm->flags.bits.lut3d_dma_enable &&
dc->hwss.trigger_3dlut_dma_load)
dc->hwss.trigger_3dlut_dma_load(dc,
pipe_ctx);
@@@ -5087,7 -5167,7 +5167,7 @@@
dc->hwss.program_triplebuffer(
dc, pipe_ctx,
pipe_ctx->plane_state->triplebuffer_flips);
}
- if
(pipe_ctx->plane_state->update_flags.bits.addr_update)
+ if
(pipe_ctx->plane_state->update_bits.addr_update)
dc->hwss.update_plane_addr(dc,
pipe_ctx);
}
}
@@@ -5178,7 -5258,7 +5258,7 @@@
if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
!pipe_ctx->stream ||
!should_update_pipe_for_stream(context, pipe_ctx, stream) ||
-
!pipe_ctx->plane_state->update_flags.bits.addr_update ||
+ !pipe_ctx->plane_state->update_bits.addr_update
||
pipe_ctx->plane_state->skip_manual_trigger)
continue;
@@@ -5617,7 -5697,7 +5697,7 @@@ static bool commit_minimal_transition_s
/* force full surface update */
for (i = 0; i < dc->current_state->stream_count; i++) {
for (j = 0; j < (unsigned
int)dc->current_state->stream_status[i].plane_count; j++) {
-
dc->current_state->stream_status[i].plane_states[j]->update_flags.raw =
0xFFFFFFFF;
+
dc_pipe_update_bits_set_full(&dc->current_state->stream_status[i].plane_states[j]->update_bits);
}
}
@@@ -5792,14 -5872,9 +5872,9 @@@ static bool full_update_required
(srf_updates[i].sdr_white_level_nits &&
srf_updates[i].sdr_white_level_nits !=
srf_updates->surface->sdr_white_level_nits) ||
srf_updates[i].in_transfer_func ||
- srf_updates[i].func_shaper ||
- srf_updates[i].lut3d_func ||
srf_updates[i].surface->force_full_update ||
(srf_updates[i].flip_addr &&
- srf_updates[i].flip_addr->address.tmz_surface
!= srf_updates[i].surface->address.tmz_surface) ||
- (srf_updates[i].cm2_params &&
-
(srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting !=
srf_updates[i].surface->mcm_shaper_3dlut_setting ||
-
srf_updates[i].cm2_params->component_settings.lut1d_enable !=
srf_updates[i].surface->mcm_lut1d_enable))))
+ srf_updates[i].flip_addr->address.tmz_surface
!= srf_updates[i].surface->address.tmz_surface)))
return true;
}
@@@ -6063,17 -6138,17 +6138,17 @@@ static bool update_planes_and_stream_v3
return true;
}
- static void clear_update_flags(struct dc_surface_update *srf_updates,
+ static void clear_update_bits(struct dc_surface_update *srf_updates,
int surface_count, struct dc_stream_state *stream)
{
int i;
if (stream)
- stream->update_flags.raw = 0;
+ stream_update_flags_clear(&stream->update_flags);
for (i = 0; i < surface_count; i++)
if (srf_updates[i].surface)
- srf_updates[i].surface->update_flags.raw = 0;
+
dc_pipe_update_bits_clear(&srf_updates[i].surface->update_bits);
}
bool dc_update_planes_and_stream(struct dc *dc,
@@@ -6125,7 -6200,7 +6200,7 @@@ void dc_commit_updates_for_stream(struc
}
if (ret && dc->ctx->dce_version >= DCN_VERSION_3_2)
- clear_update_flags(srf_updates, surface_count, stream);
+ clear_update_bits(srf_updates, surface_count, stream);
}
uint8_t dc_get_current_stream_count(struct dc *dc)
@@@ -6165,6 -6240,115 +6240,6 @@@ void dc_interrupt_ack(struct dc *dc, en
dal_irq_service_ack(dc->res_pool->irqs, src);
}
-/* Preserve this tg if a physical link is still lighting a present display */
-static bool should_preserve_tg(struct dc *dc, struct timing_generator *tg)
-{
- unsigned int i, j;
-
- /* Check if a physical link is lighting this tg */
- for (i = 0; i < dc->link_count; i++) {
- struct dc_link *link = dc->links[i];
- int fe;
-
- if (!link || link->ep_type != DISPLAY_ENDPOINT_PHY ||
- !link->link_enc ||
- !link->link_enc->funcs->is_dig_enabled ||
-
!link->link_enc->funcs->is_dig_enabled(link->link_enc) ||
- !link->link_enc->funcs->get_dig_frontend)
- continue;
-
- /* Get the DIG front-end this link's encoder drives; skip if
none */
- fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
- if (fe == ENGINE_ID_UNKNOWN)
- continue;
-
- /* Find the stream encoder bound to this link's front-end */
- for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
- struct stream_encoder *se = dc->res_pool->stream_enc[j];
-
- /* Skip unless this stream encoder feeds our front-end
and drives this tg */
- if (se->id != fe || !se->funcs->dig_source_otg ||
- (int)se->funcs->dig_source_otg(se) !=
tg->inst)
- continue;
-
- /* This link drives the OTG: keep a seamless-boot eDP,
or
- * any external link whose sink is still connected.
- */
- if (link->connector_signal == SIGNAL_TYPE_EDP)
- return true;
- if (link->link_enc->funcs->get_hpd_state &&
- dc->link_srv->get_hpd_state(link))
- return true;
- }
- }
-
- return false;
-}
-
-/*
- * GOP/vBIOS may leave an OPTC enabled for a display present at power-on but
no
- * longer driven (e.g. external DP unplugged at boot). Such a dangling pipe
keeps
- * DCN out of idle and blocks s0i3. If nothing needs to survive (no committed
- * stream or seamless-boot eDP) and no sink is still connected, power down
all hw
- * blocks.
- */
-void dc_disable_dangling_timing_generators(struct dc *dc)
-{
- struct dce_hwseq *hws = dc->hwseq;
- bool any_dangling = false;
- bool any_preserved = false;
- bool any_connected = false;
- unsigned int i;
-
- /* No real hw to touch on a virtual/emulated environment */
- if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
- return;
-
- /* Wake hw out of IPS before reading/touching tg state */
- dc_exit_ips_for_hw_access(dc);
-
- /* Classify every enabled tg as either to-preserve or dangling */
- for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
- struct timing_generator *tg =
dc->res_pool->timing_generators[i];
-
- if (!tg || !tg->funcs->is_tg_enabled ||
- !tg->funcs->is_tg_enabled(tg))
- continue;
-
- if (should_preserve_tg(dc, tg))
- any_preserved = true;
- else
- any_dangling = true;
- }
-
- /* A physically connected sink (HPD asserted) will be re-lit by a
- * subsequent atomic commit. For that case we don't call the global
- * power_down().
- */
- for (i = 0; i < dc->link_count; i++) {
- struct dc_link *link = dc->links[i];
-
- if (link && link->ep_type == DISPLAY_ENDPOINT_PHY &&
- link->link_enc && link->link_enc->funcs &&
- link->link_enc->funcs->get_hpd_state &&
- dc->link_srv->get_hpd_state(link)) {
- any_connected = true;
- break;
- }
- }
-
- if (!any_dangling)
- return;
-
- if (!any_preserved && !any_connected && hws && hws->funcs.power_down) {
- /* Truly headless / all sinks unplugged: nothing to preserve */
- DC_LOG_DC("%s: powering down dangling hw blocks to allow
idle\n",
- __func__);
- hws->funcs.power_down(dc);
- return;
- }
-}
-
/*
* dc_get_flip_pending_on_otg() - Check if a GRPH_FLIP is still pending on OTG
*
@@@ -6183,7 -6367,7 +6258,7 @@@
bool dc_get_flip_pending_on_otg(struct dc *dc, int otg_inst)
{
bool flip_pending = false;
- int i;
+ unsigned int i;
if (!dc || !dc->current_state)
return false;
@@@ -7587,7 -7771,7 +7662,7 @@@ bool dc_capture_register_software_state
struct dc_plane_state *plane_state =
pipe_ctx->plane_state;
/* MPCC blending tree and mode control - capture actual
blend configuration */
- state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type
!= TF_TYPE_BYPASS) ? 1 : 0;
+ state->mpc.mpcc_mode[i] =
(plane_state->cm.blend_func.type != TF_TYPE_BYPASS) ? 1 : 0;
state->mpc.mpcc_alpha_blend_mode[i] =
plane_state->per_pixel_alpha ? 1 : 0;
state->mpc.mpcc_alpha_multiplied_mode[i] =
plane_state->pre_multiplied_alpha ? 1 : 0;
state->mpc.mpcc_blnd_active_overlap_only[i] = 0; /*
Default - no overlap restriction */
@@@ -7920,7 -8104,7 +7995,7 @@@ struct dc_update_scratch_space
struct dc_stream_state *stream;
struct dc_stream_update *stream_update;
bool update_v3;
- bool do_clear_update_flags;
+ bool do_clear_update_bits;
enum surface_update_type update_type;
struct dc_state *new_context;
enum update_v3_flow flow;
@@@ -7963,8 -8147,8 +8038,8 @@@ static bool update_planes_and_stream_cl
const struct dc_update_scratch_space *scratch
)
{
- if (scratch->do_clear_update_flags)
- clear_update_flags(scratch->surface_updates,
scratch->surface_count, scratch->stream);
+ if (scratch->do_clear_update_bits)
+ clear_update_bits(scratch->surface_updates,
scratch->surface_count, scratch->stream);
return false;
}
@@@ -8218,8 -8402,8 +8293,8 @@@ static bool update_planes_and_stream_cl
ASSERT(false);
}
- if (scratch->do_clear_update_flags)
- clear_update_flags(scratch->surface_updates,
scratch->surface_count, scratch->stream);
+ if (scratch->do_clear_update_bits)
+ clear_update_bits(scratch->surface_updates,
scratch->surface_count, scratch->stream);
return false;
}
@@@ -8242,7 -8426,7 +8317,7 @@@ struct dc_update_scratch_space *dc_upda
.stream = stream,
.stream_update = stream_update,
.update_v3 = version >= DCN_VERSION_4_01 || version ==
DCN_VERSION_3_2 || version == DCN_VERSION_3_21,
- .do_clear_update_flags = version >= DCN_VERSION_1_0,
+ .do_clear_update_bits = version >= DCN_VERSION_1_0,
};
return scratch;
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