The RK3568 LVDS transmitter has no register block of its own: it is programmed entirely through the GRF and re-uses the MIPI DSI0 D-PHY (rockchip,rk3568-dsi-dphy) in LVDS mode. It therefore needs phys/phy-names like px30, but unlike px30 it does take a pclk (PCLK_DSITX_0, shared with the DSI controller the D-PHY belongs to).
It has no analog supplies of its own and no pinctrl: the lanes are dedicated D-PHY pins, not muxable GPIOs. Signed-off-by: Rok Markovic <[email protected]> Assisted-by: Claude:claude-opus-4-8 --- .../display/rockchip/rockchip,lvds.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml index 03b002a..6280f7e 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml @@ -15,6 +15,7 @@ properties: enum: - rockchip,px30-lvds - rockchip,rk3288-lvds + - rockchip,rk3568-lvds reg: maxItems: 1 @@ -121,6 +122,27 @@ allOf: - avdd1v8-supply - avdd3v3-supply + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-lvds + + then: + properties: + reg: false + avdd1v0-supply: false + avdd1v8-supply: false + avdd3v3-supply: false + pinctrl-names: false + pinctrl-0: false + + required: + - clocks + - clock-names + - phys + - phy-names + additionalProperties: false examples: -- 2.43.0
