The GXLX2 HDMI transmitter uses the byte-addressed DesignWare controller registers and directly mapped TOP window also present on G12A. Its display pipeline and HDMI PHY programming remain GXL-like, however.
Add a dedicated compatible with no fallback. The generic meson-gx-dw-hdmi interface uses indirect address/data registers and cannot operate this hardware, while meson-g12a-dw-hdmi would select incompatible PHY initialization values. The one-resource representation is proposed for RFC review; DWC and TOP occupy one contiguous MMIO range on the tested HG680-LC. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Zinan Zhou <[email protected]> --- .../devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml index 416fe263ac92..4a17eccabea9 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml @@ -29,8 +29,10 @@ description: | The HDMI TOP block only supports HPD sensing. The Synopsys HDMI Controller interrupt is routed through the TOP Block interrupt. - Communication to the TOP Block and the Synopsys HDMI Controller is done - via a pair of dedicated addr+read/write registers. + Communication with the TOP Block and the Synopsys HDMI Controller uses a pair + of dedicated address/data registers on GXBB, GXL and GXM. GXLX2 and G12A + instead expose byte-addressed controller registers and a directly mapped TOP + window. The HDMI PHY is configured by registers in the HHI register block. Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux @@ -54,6 +56,7 @@ properties: - amlogic,meson-gxm-dw-hdmi # GXM (S912) - const: amlogic,meson-gx-dw-hdmi - enum: + - amlogic,meson-gxlx2-dw-hdmi # GXLX2 (S905L3) - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2) reg: -- 2.43.0
