Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
Pre-existing issues: - [High] The patch attempts to fix spurious completions from timed-out AUX transfers by adding `reinit_completion()`, but the fix is insufficient due to a TOCTOU race with the driver's threaded IRQ handler. - [High] The driver fails to support DP AUX short reads, incorrectly rejecting them with -EBUSY instead of returning the number of bytes successfully transferred, which breaks I2C-over-AUX. - [High] Missing hardware reset on AUX transfer timeout leaves the controller in an undefined/busy state. - [High] The DP AUX channel and I2C adapter are registered and exposed before the hardware is initialized and interrupts are enabled, causing early access to fail with timeouts. - [High] DP AUX transfers can execute with the PHY powered off, leading to hardware timeouts or crashes. -- --- Patch [4]: [PATCH v6 04/16] drm/bridge: synopsys: dw-dp: Add missing reinit_completion --- commit fc6159d600f530845f6f08962e449b720526ee08 Author: Sebastian Reichel <[email protected]> drm/bridge: synopsys: dw-dp: Add missing reinit_completion This patch adds a reinit_completion call before sending an AUX command to prevent subsequent transfers from immediately triggering if an earlier one timed out and the interrupt fired later. > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c > b/drivers/gpu/drm/bridge/synopsys/dw-dp.c > index b28040d69fabf..2f0ee7ab7febd 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c > @@ -1465,6 +1465,8 @@ static ssize_t dw_dp_aux_transfer(struct drm_dp_aux > *aux, > if (WARN_ON(msg->size > 16)) > return -E2BIG; > > + reinit_completion(&dp->complete); > + [Severity: High] This isn't a bug introduced by this patch, but the attempt to fix the spurious completions seems incomplete due to a race condition. Because reinit_completion is called locklessly here, could the threaded IRQ handler execute concurrently? If dw_dp_irq is processing a delayed interrupt from a previous timeout: dw_dp_irq() { ... complete(&dp->complete); } Doesn't this mean it could call complete immediately after this reinit_completion, instantly satisfying the new wait and causing the driver to read garbage hardware status? > switch (msg->request & ~DP_AUX_I2C_MOT) { > case DP_AUX_NATIVE_WRITE: > case DP_AUX_I2C_WRITE: [Severity: High] This is a pre-existing issue, but does this driver fail to support DP AUX short reads? Later in dw_dp_aux_transfer: if (count != msg->size) return -EBUSY; If the hardware returns fewer bytes than requested, returning -EBUSY causes the DRM core helper drm_dp_i2c_do_msg to endlessly retry the exact same full-length transfer without advancing its buffer. Could this break communication with I2C devices on the DP bus? [Severity: High] This is a pre-existing issue, but is a hardware reset missing when an AUX transfer times out? In the error path of dw_dp_aux_transfer: if (!status) { dev_err(dp->dev, "timeout waiting for AUX reply\n"); return -ETIMEDOUT; } If wait_for_completion_timeout expires, returning -ETIMEDOUT without resetting the underlying AUX controller or clearing the pending state might leave the hardware state machine permanently stuck. Will subsequent transfers fail because the hardware is still busy? [Severity: High] This isn't a bug introduced by this patch, but is the AUX channel registered before interrupts are enabled? Looking at dw_dp_bind, the channel is registered early: ret = drm_dp_aux_register(&dp->aux); But interrupts are enabled much later in the same function: enable_irq(dp->irq); If a userspace tool like ddcutil or an I2C auto-prober attempts a transaction in this window, won't dw_dp_aux_transfer fail because the hardware cannot yet generate interrupts? [Severity: High] This is a pre-existing issue, but can DP AUX transfers execute with the PHY powered off? Direct accesses from userspace via the character device call directly into: static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) Internal callers wrap this to ensure the PHY is powered on: dw_dp_bridge_edid_read() { ... ret = phy_power_on(dp->phy); if (ret) return NULL; edid = drm_edid_read_ddc(connector, &dp->aux.ddc); phy_power_off(dp->phy); ... } Since dw_dp_aux_transfer itself doesn't check or manage the PHY power state, could a direct userspace access while the display is suspended cause MMIO timeouts or system crashes? -- Sashiko AI review ยท https://sashiko.dev/#/patchset/20260724-synopsys-dw-dp-improvements-v6-0-041d99a19...@collabora.com?part=4
