Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] The newly added clock names in the device tree binding do not match the `fw_name` expected by the clock driver, breaking parent clock resolution. --
--- Patch [4]: [PATCH 04/17] dt-bindings: soc: spacemit: allow eDP/DP PHY PLL pixel clocks on K3 APMU --- commit 4027b4adb6d5e7a26089ca7f70a25150faf1098a Author: Cody Kang <[email protected]> dt-bindings: soc: spacemit: allow eDP/DP PHY PLL pixel clocks on K3 APMU The APMU's eDP pixel-clock muxes select the DP PHY PLLs as parents, so the K3 syscon takes two clock inputs the other variants do not have. > diff --git > a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml > b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml > index d3a7c93c3c54f..b8fc6632a3928 100644 > --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml > +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml [ ... ] > @@ -31,14 +31,18 @@ properties: > maxItems: 1 > > clocks: > - maxItems: 4 > + minItems: 4 > + maxItems: 6 > > clock-names: > + minItems: 4 > items: > - const: osc > - const: vctcxo_1m > - const: vctcxo_3m > - const: vctcxo_24m > + - const: edp0_pll_pxclk > + - const: edp1_pll_pxclk [Severity: High] Will this mismatch with the clock driver's expected firmware names? Looking at edp0_pclk_parents in drivers/clk/spacemit/ccu-k3.c, the driver hardcodes the expected device tree string as "external_clk": drivers/clk/spacemit/ccu-k3.c:edp0_pclk_parents[] = { ... CCU_PARENT_NAME(external_clk), ... }; Since this binding strictly mandates "edp0_pll_pxclk" and "edp1_pll_pxclk" instead of "external_clk", the Common Clock Framework will search the clock-names array for "external_clk" and fail to resolve the parent clocks for the eDP pixel clock muxes. -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=4
