On Tue, Aug 4, 2026 at 12:11 AM Jernej Skrabec <[email protected]> wrote: > > The 8-bit entry of the last MPLL row (594 MHz) doesn't lock reliably on > H6. 4K@60 RGB/YUV444, which is the mode that reaches this entry, doesn't > come up. > > Align the value with the vendor driver. Other entries are left alone, > they are used by lower pixel clocks which work fine. > > Tested with 4K@60 on a LG TV. > > Fixes: 0fb4b858b102 ("drm/sun4i: Add support for H6 HDMI PHY") > Signed-off-by: Jernej Skrabec <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]> > --- > drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c > b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c > index 4fa69c463dc4..489ea94693ff 100644 > --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c > +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c > @@ -91,7 +91,7 @@ static const struct dw_hdmi_mpll_config > sun50i_h6_mpll_cfg[] = { > }, > }, { > 594000000, { > - { 0x1a40, 0x0003 }, > + { 0x1a7c, 0x0003 }, > { 0x3b4c, 0x0003 }, > { 0x5a64, 0x0003 }, > }, > -- > 2.43.0 >
