On Wed, Jul 29, 2026 at 01:54:54PM +0100, Biju wrote: > From: Biju Das <[email protected]> > > Move the DSIDPHYCTRL0 initialization value into the hw_info structure as > dphyctrl0_init_val, allowing SoC-specific D-PHY control register > initialization to be defined per compatible. This prepares the driver for > supporting SoCs that require a different initial DSIDPHYCTRL0 value. >
Reviewed-by: Tommaso Merciai <[email protected]> Kind regards, Tommaso > Signed-off-by: Biju Das <[email protected]> > --- > v1->v2: > * No change. > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > index 0590ade96b91..2128fd16ebc9 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -56,6 +56,7 @@ struct rzg2l_mipi_dsi_hw_info { > } cpg_plldsi; > u32 phy_reg_offset; > u32 link_reg_offset; > + u32 dphyctrl0_init_val; > unsigned long min_dclk; > unsigned long max_dclk; > u8 features; > @@ -493,9 +494,7 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi > *dsi, > } > > /* Initializing DPHY before accessing LINK */ > - dphyctrl0 = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | DSIDPHYCTRL0_CMN_MASTER_EN | > - DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | DSIDPHYCTRL0_EN_BGR; > - > + dphyctrl0 = dsi->info->dphyctrl0_init_val; > rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0); > usleep_range(20, 30); > > @@ -1531,6 +1530,8 @@ static const struct rzg2l_mipi_dsi_hw_info > rzg2l_mipi_dsi_info = { > .dphy_exit = rzg2l_mipi_dsi_dphy_exit, > .dphy_conf_clks = rzg2l_dphy_conf_clks, > .link_reg_offset = 0x10000, > + .dphyctrl0_init_val = DSIDPHYCTRL0_CAL_EN_HSRX_OFS | > DSIDPHYCTRL0_CMN_MASTER_EN | > + DSIDPHYCTRL0_RE_VDD_DETVCCQLV18 | > DSIDPHYCTRL0_EN_BGR, > .min_dclk = 5803, > .max_dclk = 148500, > }; > -- > 2.43.0 >
