On Tue Aug 4, 2026 at 1:23 PM BST, Link Mauve wrote:
> Hi,
>
> On Mon, Aug 03, 2026 at 03:34:37PM +0200, Laura Nao wrote:
>> Add a threaded IRQ wrapper for Tyr interrupt sources and use it to
>> handle the firmware Job IRQ.
>>
>> The Job IRQ reports requests from the CSF firmware, including global
>> interface requests and CSG attention bits. Only the GLB bit is currently
>> handled, as it will be used to check firmware readiness. CSG bits
>> handling will be added at a later stage. Add a Job IRQ handler that
>> masks the interrupt in the primary IRQ handler, processes pending raw
>> status in the threaded handler, clears the handled bit, and reenables
>> the mask before returning.
>> Add a wait queue and a bool flag so the handler can signal firmware
>> readiness when the GLB bit is set.
> […]
>> diff --git a/drivers/gpu/drm/tyr/fw/irq.rs b/drivers/gpu/drm/tyr/fw/irq.rs
>> new file mode 100644
>> index 000000000000..6eeb1399a7b3
>> --- /dev/null
>> +++ b/drivers/gpu/drm/tyr/fw/irq.rs
>> @@ -0,0 +1,105 @@
> […]
>> +/// Requests a threaded IRQ registration for the Job IRQ.
>> +///
>> +/// # Safety
>> +///
>> +/// Callers must not `mem::forget()` the resulting registration or
>> otherwise prevent its
>> +/// [`Drop`] implementation from running.
>> +pub(crate) unsafe fn job_irq_init<'a>(
>> + pdev: &'a platform::Device<Bound>,
>> + iomem: Arc<IoMem<'a>>,
>> + fw_ready: Arc<AtomicBool>,
>> + job_irq_wait: Arc<WaitQueue>,
>> +) -> Result<impl PinInit<ThreadedRegistration<'a, TyrIrq<JobIrq<'a>>>,
>> Error> + 'a> {
>> + iomem.write_reg(JOB_IRQ_MASK::zeroed().with_glb(true));
>> + let job_irq = JobIrq {
>> + iomem: iomem.clone(),
>> + fw_ready,
>> + job_irq_wait,
>> + };
>> + // SAFETY: The caller guarantees the resulting registration will not be
>> leaked.
>> + unsafe { TyrIrq::request(pdev, c_str!("job"), job_irq) }
>
> Nowadays we use the shorter c"job" way of creating a &CStr, and I think
> the macro will even generate warnings in some configurations (perhaps
> CLIPPY=1?).
klint will produce a warning for this, but clippy won't.
Best,
Gary
>
>> +}
>> +
>> +impl TyrIrqTrait for JobIrq<'_> {
>> + fn read_status(&self) -> u32 {
>> + self.iomem.read(JOB_IRQ_STATUS).into_raw()
>> + }
>> +
>> + fn clear_mask(&self) {
>> + self.iomem.write_reg(JOB_IRQ_MASK::zeroed());
>> + }
>> +
>> + fn reenable_mask(&self) {
>> + self.iomem.write_reg(JOB_IRQ_MASK::zeroed().with_glb(true));
>> + }
>> +
>> + fn read_raw_status(&self) -> u32 {
>> + self.iomem.read(JOB_IRQ_RAWSTAT).into_raw()
>> + }
>> +
>> + fn clear_status(&self, status: u32) {
>> + self.iomem.write_reg(JOB_IRQ_CLEAR::from_raw(status));
>> + }
>> +
>> + fn mask(&self) -> u32 {
>> + JOB_IRQ_MASK::zeroed().with_glb(true).into_raw()
>> + }
>> +
>> + fn handle(&self, status: u32) {
>> + // TODO: handle other Job IRQ events (e.g. CSG attention bits) here
>> once
>> + // support for them is added.
>> + if JOB_IRQ_RAWSTAT::from_raw(status).glb() {
>> + self.fw_ready.store(true, Ordering::Release);
>> + self.job_irq_wait.wake_ua/rust/macros/module.rsp_all();
>> + }
>> + }
>> +}
>>
>> ---
>> base-commit: 98ae54f97175c4992b4e5bff53f3c6bc24f0f491
>> change-id: 20260728-tyr-irq-v2-0b3c5022be33
>>
>> Best regards,
>> --
>> Laura Nao <[email protected]>
>>
>>
