On Sat, 25 Jul 2026 00:51:11 -0400, Cody Kang wrote: > The SpacemiT K3 DisplayPort controller drives its four transmit lanes > through an integrated Innosilicon DP PHY, one PHY per controller. Add a > binding so the controller can reference its transmit PHY and the pixel > clock the PHY's PLL sources. > > The PHY's registers are interleaved with its parent controller's inside > one MMIO window, so it owns neither a reg nor a reset and is modelled as > a child of the controller. > > It exposes its PLL-generated pixel clock through #clock-cells, so the > APMU pixel-clock mux can select it as a parent through the clock > framework. > > Signed-off-by: Cody Kang <[email protected]> > --- > .../bindings/phy/spacemit,k3-inno-dp-phy.yaml | 48 > ++++++++++++++++++++++ > 1 file changed, 48 insertions(+) >
Reviewed-by: Rob Herring (Arm) <[email protected]>
