From: Chaoyi Chen <[email protected]> This series is dedicated to enhancing the DSI controller and PHY timing interaction, refining the lane rate calculation, and addressing the associated hardware limitations.
Changes in v4: - Link to v3: https://lore.kernel.org/all/[email protected]/ - Add missing RK3506 timing and the fallback path for get_timing (sashiko). - Fix potential overflow and underflow issues in bandwidth calculation(sashiko). Changes in v3: - Link to v2: https://lore.kernel.org/all/[email protected]/ - Rebase to Linux v7.2 Changes in v2: - Link to v1: https://lore.kernel.org/all/[email protected]/ - Fix the unit conversion for max_mbps. - Split the lane rate calculation into a separate patch. - Add more comment about timing config. Chaoyi Chen (3): drm/rockchip: dsi: Add maximum per lane bit rate calculation drm/rockchip: dsi: Add dphy_get_timing support for multiple PHY types drm/rockchip: dsi: Relax the lane rate margin requirements .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 70 +++++++++++++++++-- 1 file changed, 64 insertions(+), 6 deletions(-) -- 2.53.0
