On Thu, Aug 13, 2026 at 3:51 PM Taimuraz Kaitmazov <[email protected]> wrote: > > (Resending to the list -- my earlier copy went to Alex alone.) > > On 8/13/26 21:54, Alex Deucher wrote: > > PCIe transactions from the device should snoop the CPU's cache. > > That is what I assumed too, but it is not what I measure on npu4. Leaving a > new input dirty in the CPU and running, the array computes on the previous > contents, each out of 20 runs. Flushing that same input and running again, it > sees it - so the data does reach the buffer, and something is not picking up > the dirty line. > > What I cannot square is that ubuf maps with dma_map_sgtable() and nothing > else, and on x86 the DMA API no-ops the syncs, so that path looks correct > only because SYNC_BO clflushes on top of it. > > Is the array expected to snoop on this part? Happy to run whatever would > settle it, or to be told what I am measuring wrong.
The snoop should be part of the DMA from the device. By default PCI devices are supposed to snoop CPU caches, and there is the option of doing non-snooped transactions if the platform supports it. It certainly sounds like these are non-snooped from what you've said. I wonder if there is some device config option to enable snooped vs. non-snooped DMAs? If not, then either you'd need to allocate non-cached memory or you'll need to flush the caches appropriately. Alex
