Hello Svyatoslav, On Thu Jun 25, 2026 at 10:25 AM CEST, Svyatoslav Ryhel wrote: > After tc358768_setup_pll() enables PLL_CKEN and the lock indicator comes > up, the DSI register sequence runs near immediately. On TF700T this
Do you refer to the Asus Transformer Pad TF700T here? Please add the full name of the device. > results in the bridge claiming PLL lock but producing no DSI video output: > the panel powers up, the backlight comes on, but the framebuffer is never > scanned out. > > Insert a small settling delay between PLL setup and the rest of the > attach. > > Suggested-by: Michele Brocco <[email protected]> > Tested-by: Michele Brocco <[email protected]> # TF700T > Signed-off-by: Svyatoslav Ryhel <[email protected]> > --- > drivers/gpu/drm/bridge/tc358768.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/tc358768.c > b/drivers/gpu/drm/bridge/tc358768.c > index 0f2820b37302..ea358c8da0e9 100644 > --- a/drivers/gpu/drm/bridge/tc358768.c > +++ b/drivers/gpu/drm/bridge/tc358768.c > @@ -824,6 +824,9 @@ static void tc358768_bridge_atomic_pre_enable(struct > drm_bridge *bridge, > return; > } > > + /* Allow the PLL to settle */ > + mdelay(20); Why 20 ms, and not another amount? Is it backed by some datasheet? Or just "it's what fixed my usecase"? The extra delay is a panel requirement maybe, and definitely specific to the specific hardware pipeline of the TF700T. Would it make sense to add a DT property so only hardware needing a delay can add it, and add as much as needed? Luca -- Luca Ceresoli, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
