On Thu Aug 20, 2026 at 2:28 AM JST, Gary Guo wrote: > In the GSP->CPU messaging path, the code reads the write pointer from GSP, > reads the response and advances the read pointer. > > A LOAD->LOAD ordering is required after the write pointer read and the data > read. Add it as this is currently missing. > > A LOAD->STORE ordering is required after the data read and the advance of > read pointer. Currently a Rust `SeqCst` barrier is used, which roughly maps > to `smp_mb(Full)`; this however does not order DMA operations (notably on > ARM, the generate barrier orders inner shareable and not outer shareable, > which is ordered by `dma_mb`). This ordering does not need to be in between > read pointer read and write, because it's for ordering between the ring > buffer data and the pointer; the RMW operation does not internally need a > barrier (nor it has to be atomic, as CPU pointers are updated by CPU only), > so move it to before the RMW sequence for clarity. > > Signed-off-by: Gary Guo <[email protected]> > ---
Reviewed-by: Eliot Courtney <[email protected]>
