On 8/17/2026 10:14 PM, Konrad Dybcio wrote:
On 8/17/26 4:13 PM, Konrad Dybcio wrote:
On 8/13/26 9:44 AM, Yongxing Mou wrote:
On 7/20/2026 4:49 PM, Konrad Dybcio wrote:
On 7/20/26 10:43 AM, Yongxing Mou wrote:
Kaanapali (SM8750) and Glymur use two display power domains.
CORE_GDSC powers the main display hardware while INT2_GDSC
powers a subset of SSPP blocks.
Can they operate independently? Does INT2_GDSC need to be
powered on after CORE_GDSC?
On Kaanapali, my understanding is that CORE_GDSC and INT2_GDSC should generally
track the same state, except that INT2_GDSC may be powered down when SSPP1
(VIG2/VIG3/DMA5) is unused.
Is the MDSS any useful if *only* INT2_GDSC is enabled? Can the INT2_GDSC
be enabled itself if CORE_GDSC is off?
(I didn't quite know how to parse the list of states you provided in your
reply so I asked again)
Konrad
Hi, Konard. Would you recommend adding the parent clock in the clock
driver, or handling 2 GDSC in the display driver? I'm preparing the next
revision and would appreciate your feedback.
