> -----Original Message----- > From: Intel-gfx <[email protected]> On Behalf Of > Chaitanya > Kumar Borah > Sent: Tuesday, August 4, 2026 6:01 PM > To: [email protected]; [email protected]; dri- > [email protected] > Cc: Borah, Chaitanya Kumar <[email protected]> > Subject: [v6 5/9] drm/i915/display: Program CSC on SDR planes based on Fixed > Matrix Colorop > > When a color pipeline is active, program the SDR plane fixed-function CSC > based > on the Fixed Matrix Colorop's state. Re-use the existing plane state > variables for > color_range and color_encoding. Track the bypass state explicitly as a boolean > since bypass is managed separately from the FIXED_MATRIX enum value in the > colorop framework. Keep the programming based on color_encoding/color_range > legacy properties intact. Looks Good to me. Reviewed-by: Uma Shankar <[email protected]> > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_plane.c | 53 ++++++++++++++++++- > .../drm/i915/display/skl_universal_plane.c | 4 +- > 3 files changed, 55 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 20a07ea06b5e..beb0169cabef 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -683,6 +683,7 @@ struct intel_plane_state { > enum drm_color_range color_range; > enum drm_scaling_filter scaling_filter; > struct drm_property_blob *ctm, *degamma_lut, *gamma_lut, > *lut_3d; > + bool csc_ff_enable; > } hw; > > struct i915_vma *ggtt_vma; > diff --git a/drivers/gpu/drm/i915/display/intel_plane.c > b/drivers/gpu/drm/i915/display/intel_plane.c > index d0f99a87c42e..25ca049009ef 100644 > --- a/drivers/gpu/drm/i915/display/intel_plane.c > +++ b/drivers/gpu/drm/i915/display/intel_plane.c > @@ -462,6 +462,42 @@ intel_plane_colorop_replace_blob(struct > intel_plane_state *plane_state, > return false; > } > > +static u32 > +fixedmatrix_colorop_to_encoding(enum drm_colorop_fixed_matrix_type > +fm_type) { > + switch (fm_type) { > + case DRM_COLOROP_FM_YCBCR709_FULL_RGB: > + case DRM_COLOROP_FM_YCBCR709_LIMITED_RGB: > + return DRM_COLOR_YCBCR_BT709; > + > + case DRM_COLOROP_FM_YCBCR2020_NC_FULL_RGB: > + case DRM_COLOROP_FM_YCBCR2020_NC_LIMITED_RGB: > + return DRM_COLOR_YCBCR_BT2020; > + > + case DRM_COLOROP_FM_YCBCR601_FULL_RGB: > + case DRM_COLOROP_FM_YCBCR601_LIMITED_RGB: > + default: > + return DRM_COLOR_YCBCR_BT601; > + } > +} > + > +static u32 > +fixedmatrix_colorop_to_range(enum drm_colorop_fixed_matrix_type > +fm_type) { > + switch (fm_type) { > + case DRM_COLOROP_FM_YCBCR601_FULL_RGB: > + case DRM_COLOROP_FM_YCBCR709_FULL_RGB: > + case DRM_COLOROP_FM_YCBCR2020_NC_FULL_RGB: > + return DRM_COLOR_YCBCR_FULL_RANGE; > + > + case DRM_COLOROP_FM_YCBCR601_LIMITED_RGB: > + case DRM_COLOROP_FM_YCBCR709_LIMITED_RGB: > + case DRM_COLOROP_FM_YCBCR2020_NC_LIMITED_RGB: > + default: > + return DRM_COLOR_YCBCR_LIMITED_RANGE; > + } > +} > + > static void > intel_plane_color_copy_uapi_to_hw_state(struct intel_atomic_state *state, > struct intel_plane_state *plane_state, > @@ > -474,6 +510,7 @@ intel_plane_color_copy_uapi_to_hw_state(struct > intel_atomic_state *state, > struct drm_property_blob *blob; > struct intel_crtc_state *new_crtc_state = state ? > intel_atomic_get_new_crtc_state(state, crtc) : NULL; > + enum drm_colorop_fixed_matrix_type fm_type; > bool changed = false; > int i = 0; > > @@ -485,11 +522,23 @@ intel_plane_color_copy_uapi_to_hw_state(struct > intel_atomic_state *state, > while (iter_colorop) { > for_each_new_colorop_in_state(&state->base, colorop, > new_colorop_state, i) { > if (new_colorop_state->colorop == iter_colorop) { > - blob = new_colorop_state->bypass ? NULL : > new_colorop_state->data; > intel_colorop = to_intel_colorop(colorop); > - changed |= > intel_plane_colorop_replace_blob(plane_state, > + if (intel_colorop->id == > INTEL_PLANE_CB_CSC_FF) { > + fm_type = new_colorop_state- > >fixed_matrix_type; > + > + plane_state->hw.csc_ff_enable = > + !new_colorop_state->bypass; > + plane_state->hw.color_encoding = > + > fixedmatrix_colorop_to_encoding(fm_type); > + plane_state->hw.color_range = > + > fixedmatrix_colorop_to_range(fm_type); > + } else { > + blob = new_colorop_state->bypass ? > + NULL : new_colorop_state->data; > + changed |= > intel_plane_colorop_replace_blob(plane_state, > > intel_colorop, > > blob); > + } > } > } > iter_colorop = iter_colorop->next; > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 73be4c6ff1d3..222c3b6bbe46 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -1245,9 +1245,11 @@ static u32 glk_plane_color_ctl_input_csc(const struct > intel_plane_state *plane_s > struct intel_display *display = to_intel_display(plane_state); > const struct drm_framebuffer *fb = plane_state->hw.fb; > struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); > + bool color_pipeline = !!plane_state->uapi.color_pipeline; > + bool needs_csc = color_pipeline ? plane_state->hw.csc_ff_enable : > +fb->format->is_yuv; > u32 ctl = 0; > > - if (!fb->format->is_yuv) > + if (!needs_csc) > return 0; > > if (!icl_is_hdr_plane(display, plane->id)) { > -- > 2.50.1
