This series brings a few patches fixing horizontal sync timing, EOTP packet
behavior and hsync/vsync polarity selection when using DCSS endpoint, as
well as a small fix to properly handle if/when nwl_dsi_mode_set() fails.
The 3rd commit ("Correct auto-insert EOTP behavior") is taken directly from
NXP vendor tree, so I have kept Author unchanged, although I have modified
the commit message. Let me know if I should change Author for that.
Signed-off-by: Esben Haabendal <[email protected]>
---
Changes in v4:
- Change calculation of hfp/hbp/hsa to use the raw clock rates directly to
eliminate intermediate rounding errors.
- Drop patch 4 (will be included in follow-up patch series, together with
a patch addressing the unblanced resource teardown and PM runtime
underflow problems in the error path).
- Link to v3:
https://patch.msgid.link/[email protected]
Changes in v3:
- Added Fixes and Cc: stable tags.
- Split patch 1 into two, with change of endpoint mux control in a separate
patch.
- Fixed mux_control_try_select() state argument.
- Link to v2:
https://patch.msgid.link/[email protected]
Changes in v2:
- Added safeguard against small horizontal sync timings, protecting against
division by zero and integer underflow.
- Added error handling of nwl_dsi_mode_set() call.
- Link to v1:
https://patch.msgid.link/[email protected]
To: Andrzej Hajda <[email protected]>
To: Neil Armstrong <[email protected]>
To: Robert Foss <[email protected]>
To: Laurent Pinchart <[email protected]>
To: Jonas Karlman <[email protected]>
To: Jernej Skrabec <[email protected]>
To: Luca Ceresoli <[email protected]>
To: Maarten Lankhorst <[email protected]>
To: Maxime Ripard <[email protected]>
To: Thomas Zimmermann <[email protected]>
To: David Airlie <[email protected]>
To: Simona Vetter <[email protected]>
To: Guido Günther <[email protected]>
To: Fabio Estevam <[email protected]>
To: Robert Chiras <[email protected]>
To: Sam Ravnborg <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
Esben Haabendal (3):
drm/bridge: nwl-dsi: Cleanup endpoint mux control selection
drm/bridge: nwl-dsi: Limit LCDIF specific sync override
drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing
Robert Chiras (1):
drm/bridge: nwl-dsi: Correct auto-insert EOTP behavior
drivers/gpu/drm/bridge/nwl-dsi.c | 87 ++++++++++++++++++++++++++++++++++------
1 file changed, 74 insertions(+), 13 deletions(-)
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260710-nwl-dsi-fixes-c148b0adb685
Best regards,
--
Esben Haabendal <[email protected]>
