On Tue, Sep 1, 2026 at 9:07 AM Danilo Krummrich <[email protected]> wrote:
>
> On 8/22/26 6:42 AM, Aaron Kling via B4 Relay wrote:
> > From: Faith Ekstrand <[email protected]>
> >
> > On Tegra devices, uncached maps traslate to device memory, causing
> > unaligned accesses by userspace resulting in a SIGBUS. Instead, use
> > write-combined maps to ensure proper access.
> >
> > This would also affect discrete cards on any Arm device. It was
> > determined that discrete cards regardless of cpu arch should use
> > write-combined maps for coherent anyways. Thus this change is made for
> > all gpu types.
> >
> > Signed-off-by: Faith Ekstrand <[email protected]>
> > Co-developed-by: Aaron Kling <[email protected]>
> > Signed-off-by: Aaron Kling <[email protected]>
> Can you please provide a Fixes: tag? Also, please remember to Cc: stable if
> necessary.
Looks like the tag is:
Fixes: 1b4ea4c5980f ("drm/ttm: set the tt caching state at creation time")
Should I send another revision just to add this, or can the subsystem
maintainer add it when picking the change up? For stable, I would like
to see this picked to 6.18 at least, since I primarily work with LTS
forks.
Aaron
