The F0 command pair in this driver is already documented as enabling and disabling level 2 commands. Replace the raw writes with the shared level 2 test key helpers.
Assisted-by: LLM Signed-off-by: Linus Walleij <[email protected]> --- drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c b/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c index ca5cad41ff1d..e816783081c2 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c @@ -13,6 +13,8 @@ #include <drm/drm_modes.h> #include <drm/drm_panel.h> +#include "panel-samsung-dsi.h" + struct s6e88a0_ams452ef01 { struct drm_panel panel; struct mipi_dsi_device *dsi; @@ -43,7 +45,7 @@ static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx) dsi->mode_flags |= MIPI_DSI_MODE_LPM; - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands + samsung_dsi_test_key_on_lvl2(&dsi_ctx); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcc, 0x4c); // set Pixel Clock Divider polarity mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); @@ -66,7 +68,7 @@ static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx) mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0x2c, 0x0b); // set default elvss voltage mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf7, 0x03); // gamma/aor update - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands + samsung_dsi_test_key_off_lvl2(&dsi_ctx); mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); -- 2.55.0
