On 26-09-03 15:19:10, Dmitry Baryshkov wrote: > DSI 6G v2.9 hosts (SM8650, SM8750, Kaanapali, etc.) reparent the byte and > pixel RCGs to the DSI PHY PLL at runtime from > dsi_link_clk_set_rate_6g_v2_9(), after the PHY has been enabled. However > dsi_calc_clk_rate_6g() runs earlier, in order to compute the bit clock > request for the PHY. At that point the byte RCG still has its reset > parent (XO), so clk_round_rate() returns a bogus rate, which then ends up > in the PHY bit clock request and the PLL gets programmed to a wrong > frequency, breaking the panel. > > Move the rounding to dsi_link_clk_set_rate_6g(), which is called after > the RCGs have been reparented to the PLL. Storing the rounded rate at > this point still makes later link_clk_set_rate() calls no-ops in the > CCF. Derive the byte interface clock rate from the rounded byte clock > rate, otherwise it would keep requesting the idealized rate and > retrigger the PLL on every transfer. > > Reported-by: Abel Vesa <[email protected]> > Reported-by: Krzysztof Kozlowski <[email protected]> > Fixes: 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to the > PLL-achievable value") > Assisted-by: LLM > Signed-off-by: Dmitry Baryshkov <[email protected]>
Tested on Eliza MTP. Tested-by: Abel Vesa <[email protected]> Reviewed-by: Abel Vesa <[email protected]>
