Some TUXEDO devices have random rare hard resets during video streaming. Disabling rc6 fixes this. Until the root cause is found this is a pragmatic workaround.
Signed-off-by: Werner Sembach <[email protected]> --- drivers/gpu/drm/i915/i915_pci.c | 11 +++++++++++ include/drm/intel/pciids.h | 22 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 2f03f95945f1b..a52b56bedcf4f 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -687,6 +687,16 @@ static const struct intel_device_info adl_p_info = { .dma_mask_size = 39, }; +static const struct intel_device_info adl_p_tux_ibp8_quirk_info = { + GEN12_FEATURES, + PLATFORM(INTEL_ALDERLAKE_P), + .platform_engine_mask = + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), + .__runtime.ppgtt_size = 48, + .dma_mask_size = 39, + .has_rc6 = 0, +}; + #undef GEN #define XE_HP_PAGE_SIZES \ @@ -863,6 +873,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_info), INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_info), INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_info), + INTEL_RPLP_TUX_IBP8_QUIRK_IDS(INTEL_VGA_DEVICE, &adl_p_tux_ibp8_quirk_info), INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_info), INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_info), INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_info), diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h index 7a4a5658942d2..e4f74916a62c2 100644 --- a/include/drm/intel/pciids.h +++ b/include/drm/intel/pciids.h @@ -712,6 +712,28 @@ MACRO__(0xA7AC, ## __VA_ARGS__), \ MACRO__(0xA7AD, ## __VA_ARGS__) +#define INTEL_RPLP_TUX_IBP8_QUIRK_IDS(MACRO__, ...) \ + MACRO__##_SUB(0xA720, 0x1D05, 0x124A, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA720, 0x1D05, 0x124C, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA720, 0x1D05, 0x124E, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA720, 0x1D05, 0x130F, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7A0, 0x1D05, 0x124A, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7A0, 0x1D05, 0x124C, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7A0, 0x1D05, 0x124E, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7A0, 0x1D05, 0x130F, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7A8, 0x1D05, 0x124A, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7A8, 0x1D05, 0x124C, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7A8, 0x1D05, 0x124E, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7A8, 0x1D05, 0x130F, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7AA, 0x1D05, 0x124A, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7AA, 0x1D05, 0x124C, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7AA, 0x1D05, 0x124E, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7AA, 0x1D05, 0x130F, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7AB, 0x1D05, 0x124A, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7AB, 0x1D05, 0x124C, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7AB, 0x1D05, 0x124E, ## __VA_ARGS__), \ + MACRO__##_SUB(0xA7AB, 0x1D05, 0x130F, ## __VA_ARGS__) + /* RPL-P */ #define INTEL_RPLP_IDS(MACRO__, ...) \ MACRO__(0xA720, ## __VA_ARGS__), \ -- 2.43.0
