Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] Unconditional use of mmput_async() breaks compilation and linking on NOMMU configurations. --
commit 890c55fa04660dfbfe7364ac5c78b52162fca15b Author: Srinivasan Shanmugam <[email protected]> drm: Add drm_user_fence helper This commit introduces a common DRM user fence helper providing a kref-managed, MM-borrowing dma-fence-callback-to-workqueue pattern. It is used by drivers that must access userspace memory from a kthread context when a GPU fence signals. > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > index 8895ca0476d89..3557e6a8d31c9 100644 > --- a/drivers/gpu/drm/Makefile > +++ b/drivers/gpu/drm/Makefile > @@ -69,6 +69,7 @@ drm-y := \ > drm_syncobj.o \ > drm_sysfs.o \ > drm_trace_points.o \ > + drm_user_fence.o \ > drm_vblank.o \ [ ... ] > diff --git a/drivers/gpu/drm/drm_user_fence.c > b/drivers/gpu/drm/drm_user_fence.c > new file mode 100644 > index 0000000000000..f7882208a8b73 > --- /dev/null > +++ b/drivers/gpu/drm/drm_user_fence.c [ ... ] > +static void drm_user_fence_do_work(struct drm_work_fence *wfence) > +{ > + struct drm_user_fence *ufence = > + container_of(wfence, struct drm_user_fence, base); > + struct mm_struct *mm = NULL; > + > + if (mmget_not_zero(ufence->mm)) { > + mm = ufence->mm; > + kthread_use_mm(mm); > + } > + > + ufence->ops->writeback(ufence, !!mm); > + > + if (mm) { > + kthread_unuse_mm(mm); > + mmput_async(mm); /* requires CONFIG_MMU — GPU requires > MMU */ [Severity: Low] Does this unconditional call to mmput_async() break the build on systems without CONFIG_MMU? While the comment notes that the GPU requires an MMU, the drm_user_fence.o file is added unconditionally to the core DRM build in drivers/gpu/drm/Makefile. If the kernel is built with CONFIG_DRM enabled but CONFIG_MMU disabled, this will result in an implicit function declaration and an undefined reference to mmput_async() during linking. > + } > +} -- Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
